公开(公告)号：US6141237A

公开(公告)日：2000-10-31

申请号：US351563

申请日：1999-07-12

申请人： Jarrod Eliason ,  William F. Kraus

发明人： Jarrod Eliason ,  William F. Kraus

IPC分类号： G11C11/22 ,  H01L21/8246 ,  H01L27/105 ,  H03K3/356

CPC分类号： G11C11/22

摘要： A non-volatile ferroelectric latch includes a sense amplifier having at least one input/output coupled to a bit-line node, a ferroelectric storage capacitor coupled between a plate-line node and the bit-line node, and a load element coupled to the bit-line node. The sense amplifier further includes a second input/output coupled to a second bit-line node and the latch further includes a second ferroelectric storage capacitor coupled between a second plate-line node and the second bit-sine node, and a second load element coupled to the second bit-line node. The load element includes a dynamic, switched ferroelectric capacitor a static, nonswitched ferroelectric capacitor, a linear capacitor, or even a resistive load.

摘要翻译： 非挥发性铁电锁存器包括读出放大器，其具有耦合到位线节点的至少一个输入/输出，耦合在板状线节点和位线节点之间的铁电存储电容器以及耦合到该位线线路节点的负载元件 位线节点。 感测放大器还包括耦合到第二位线节点的第二输入/输出，并且锁存器还包括耦合在第二板状线节点和第二位正弦节点之间的第二铁电存储电容器，以及耦合到第二负载元件的第二负载元件 到第二位线节点。 负载元件包括动态的，开关的铁电电容器，静态的，非开关的铁电电容器，线性电容器或甚至电阻负载。

公开(公告)号：US06430093B1

公开(公告)日：2002-08-06

申请号：US09864858

申请日：2001-05-24

申请人： Jarrod Eliason ,  William F. Kraus

发明人： Jarrod Eliason ,  William F. Kraus

IPC分类号： G11C700

CPC分类号： G11C8/08 ,  G11C11/22

摘要： A boosting circuit for a ferroelectric memory using a NAND-INVERT circuit to control one electrode of a ferroelectric boosting capacitor. The other node of the capacitor is connected to the node to be boosted, which may be coupled to a word line. The NAND circuit has two inputs, one being coupled to the word line and another for receiving a timing signal. The timing input rises to initiate the boosting operation, and falls to initiate the removal of the boosted voltage. Only the selected word line in the memory array is affected as any word line remaining at a low logic level “0” will keep the inverter output clamped low. A second embodiment adds a second N-channel transistor in series with the inverter's N-channel transistor to allow for the option of floating the inverter output if it is desired to more quickly drive the word line high during its first upward transition.

摘要翻译： 一种用于使用NAND-INVERT电路来控制铁电升压电容器的一个电极的铁电存储器的升压电路。 电容器的另一个节点连接到要升压的节点，可以耦合到字线。 NAND电路具有两个输入，一个耦合到字线，另一个用于接收定时信号。 定时输入上升以启动升压操作，并降低以启动升压电压的去除。 只有在低逻辑电平“0”的任何字线都会影响存储器阵列中的选定字线，从而将变频器输出保持为低电平。 第二实施例将第二N沟道晶体管与逆变器的N沟道晶体管串联，以允许选择浮置逆变器输出，如果希望在其第一向上转换期间更快速地驱动字线高电平。

公开(公告)号：US5901088A

公开(公告)日：1999-05-04

申请号：US22106

申请日：1998-02-11

申请人： William F. Kraus

发明人： William F. Kraus

IPC分类号： G11C7/06 ,  G11C16/06

CPC分类号： G11C7/065

摘要： A cross-coupled sense amplifier includes a voltage-compensating balancing resistor serially connected between the drain of one of the P-channel transistors in the sense amplifier and the corresponding sensing/bit line node. The value of the balancing resistor is optimized so that the voltage imbalance between the P-channel transistor is minimized and sense amplifier sensitivity is maximized. A balancing resistor can also be placed in the N-channel transistors in the sense amplifier if desired. The balancing resistor in a typical application is about 100 to 200 ohms and fabricated from polysilicon.

摘要翻译： 交叉耦合读出放大器包括串联连接在读出放大器中的一个P沟道晶体管的漏极和对应的感测/位线节点之间的电压补偿平衡电阻器。 平衡电阻的值被优化，使得P沟道晶体管之间的电压不平衡最小化，并且感测放大器的灵敏度最大化。 如果需要，还可以将平衡电阻放置在读出放大器中的N沟道晶体管中。 典型应用中的平衡电阻约为100至200欧姆，由多晶硅制成。

公开(公告)号：US5804996A

公开(公告)日：1998-09-08

申请号：US799999

申请日：1997-02-13

申请人： Donald J. Verhaeghe ,  William F. Kraus ,  Yoshihiko Yasu

发明人： Donald J. Verhaeghe ,  William F. Kraus ,  Yoshihiko Yasu

IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  H01L21/822 ,  H01L27/04

CPC分类号： G01R31/31701 ,  G01R31/31721

摘要： A test mode circuit for an integrated circuit includes a high voltage detector having an input for receiving a high voltage signal, a Schmitt trigger having an input coupled to the output of the high voltage detector, a latch having an input coupled to the output of the Schmitt trigger and an output for providing a test mode signal in a test operational mode, and additional control circuitry for disabling the high voltage detector and Schmitt trigger so that substantially all of the active current flow in the high voltage detector and Schmitt trigger is eliminated in a normal operational mode. The test mode circuit further includes circuitry for preventing a reset condition in the latch during the test mode until a power-down condition occurs. A glitch filter is also included, which is interposed between the output of the Schmitt trigger and the input to the latch. An integrated circuit pin is coupled to both the test mode circuit and to other circuitry on the integrated circuit not forming part of the test mode circuit.

摘要翻译： 用于集成电路的测试模式电路包括具有用于接收高电压信号的输入的高电压检测器，具有耦合到高电压检测器的输出的输入的施密特触发器，具有耦合到输出的输入的锁存器 施密特触发器和用于在测试操作模式下提供测试模式信号的输出，以及用于禁用高电压检测器和施密特触发器的附加控制电路，使得高电压检测器和施密特触发器中的基本上所有的有功电流都被消除 正常的操作模式。 测试模式电路还包括用于在测试模式期间防止锁存器中的复位状态直到发生掉电状态的电路。 还包括一个毛刺滤波器，该滤波器介于施密特触发器的输出端和锁存器的输入端之间。 集成电路引脚耦合到测试模式电路和不形成测试模式电路的一部分的集成电路上的其他电路。

公开(公告)号：US5978251A

公开(公告)日：1999-11-02

申请号：US970522

申请日：1997-11-14

申请人： William F. Kraus ,  Donald J. Verhaeghe

发明人： William F. Kraus ,  Donald J. Verhaeghe

IPC分类号： G11C11/22 ,  G11C8/00 ,  G11C11/24

CPC分类号： G11C11/22

摘要： A method of driving a selected plate line segment in a 1T/1C memory, the method including the steps of logically combining an odd word line signal and an even word line signal to form a first logic signal, logically combining the first logic signal with a plate clock signal to form a second logic signal, latching the second logic signal, and driving the selected plate line segment with the latched second logic signal.

摘要翻译： 一种在1T / 1C存储器中驱动所选板线段的方法，所述方法包括以下步骤：逻辑地组合奇数字线信号和偶数字线信号以形成第一逻辑信号，将第一逻辑信号与 板时钟信号以形成第二逻辑信号，锁存第二逻辑信号，并用锁存的第二逻辑信号驱动所选择的板线段。

公开(公告)号：US6060919A

公开(公告)日：2000-05-09

申请号：US205033

申请日：1998-12-04

申请人： Dennis R. Wilson ,  William F. Kraus

发明人： Dennis R. Wilson ,  William F. Kraus

IPC分类号： H03K3/356 ,  H03K3/37

CPC分类号： H03K3/356104 ,  H03K3/356008

摘要： A preferred state power-up latch circuit includes first and second cross-coupled P-channel transistors coupled to a first source of supply voltage, first and second cross-coupled N-channel transistors coupled to a second source of supply voltage, the transistors being coupled together to form a latch having an output node, in which at least one of the gate lengths is unequal to the other gates lengths in order to establish a preferred state upon power-up, and the gate width of all the transistors is equal.

摘要翻译： 优选的状态上电锁存电路包括耦合到第一电源电压源的第一和第二交叉耦合P沟道晶体管，耦合到第二电源电压源的第一和第二交叉耦合N沟道晶体管，晶体管是 耦合在一起以形成具有输出节点的锁存器，其中至少一个栅极长度与其他栅极长度不相等，以便在上电时建立优选状态，并且所有晶体管的栅极宽度相等。

公开(公告)号：US5867047A

公开(公告)日：1999-02-02

申请号：US17577

申请日：1998-02-03

申请人： William F. Kraus

发明人： William F. Kraus

IPC分类号： G05F3/24 ,  H03K17/22

CPC分类号： H03K17/223 ,  G05F3/247

摘要： A power-on detect circuit includes: a resistor divider having a first node, a second node coupled to ground, and a center tap; a bandgap circuit for providing a reference voltage; a differential amplifier having a first input for receiving the reference voltage, a second input coupled to the center tap of the bandgap reference voltage circuit, and an output for providing a power-on detect signal; and a suppression circuit for coupling the first node of the resistor divider to a source of supply voltage once the reference voltage substantially achieves a stable reference voltage level. The suppression circuit has an input for receiving a trigger voltage generated in the bandgap circuit, and an output coupled to the first node of the resistor divider. The suppression circuit includes: an input section having an input for receiving the trigger voltage, and an output; a switch coupled between the source of supply voltage and the first node of the resistor divider having a control node coupled to the output of the input section; and a capacitor coupled to the control node of the switch. Both the switch and the bandgap circuit are responsive to the power-on detect signal for further reducing power consumption.

摘要翻译： 上电检测电路包括：具有第一节点，耦合到地的第二节点和中心抽头的电阻分压器; 用于提供参考电压的带隙电路; 差分放大器，具有用于接收参考电压的第一输入端，耦合到带隙基准电压电路的中心抽头的第二输入端和用于提供上电检测信号的输出端; 以及抑制电路，用于一旦参考电压基本达到稳定的参考电压电平，则将电阻分压器的第一节点耦合到电源电压源。 抑制电路具有用于接收在带隙电路中产生的触发电压的输入端和耦合到电阻分压器的第一节点的输出。 抑制电路包括：输入部分，具有用于接收触发电压的输入端和输出端; 耦合在电源电压源和电阻分压器的第一节点之间的开关具有耦合到输入部分的输出的控制节点; 以及耦合到开关的控制节点的电容器。 开关和带隙电路都响应于上电检测信号，以进一步降低功耗。

公开(公告)号：US5852376A

公开(公告)日：1998-12-22

申请号：US702363

申请日：1996-08-23

申请人： William F. Kraus

发明人： William F. Kraus

IPC分类号： G05F3/24 ,  H03K17/22 ,  H03L7/00

CPC分类号： H03K17/223 ,  G05F3/247

摘要： A power-on detect circuit includes: a resistor divider having a first node, a second node coupled to ground, and a center tap; a bandgap circuit for providing a reference voltage; a differential amplifier having a first input for receiving the reference voltage, a second input coupled to the center tap of the bandgap reference voltage circuit, and an output for providing a power-on detect signal; and a suppression circuit for coupling the first node of the resistor divider to a source of supply voltage once the reference voltage substantially achieves a stable reference voltage level. The suppression circuit has an input for receiving a trigger voltage generated in the bandgap circuit, and an output coupled to the first node of the resistor divider. The suppression circuit includes: an input section having an input for receiving the trigger voltage, and an output; a switch coupled between the source of supply voltage and the first node of the resistor divider having a control node coupled to the output of the input section; and a capacitor coupled to the control node of the switch. Both the switch and the bandgap circuit are responsive to the power-on detect signal for further reducing power consumption.

摘要翻译： 上电检测电路包括：具有第一节点，耦合到地的第二节点和中心抽头的电阻分压器; 用于提供参考电压的带隙电路; 差分放大器，具有用于接收参考电压的第一输入端，耦合到带隙基准电压电路的中心抽头的第二输入端和用于提供上电检测信号的输出端; 以及抑制电路，用于一旦参考电压基本达到稳定的参考电压电平，则将电阻分压器的第一节点耦合到电源电压源。 抑制电路具有用于接收在带隙电路中产生的触发电压的输入端和耦合到电阻分压器的第一节点的输出。 抑制电路包括：输入部分，具有用于接收触发电压的输入端和输出端; 耦合在电源电压源和电阻分压器的第一节点之间的开关具有耦合到输入部分的输出的控制节点; 以及耦合到开关的控制节点的电容器。 开关和带隙电路都响应于上电检测信号，以进一步降低功耗。

公开(公告)号：US5774392A

公开(公告)日：1998-06-30

申请号：US620799

申请日：1996-03-28

申请人： William F. Kraus ,  Dennis R. Wilson

发明人： William F. Kraus ,  Dennis R. Wilson

IPC分类号： G11C14/00 ,  G11C11/22 ,  G11C11/24

CPC分类号： G11C11/22

摘要： A ferroelectric memory array includes a word line coupled to a row of ferroelectric memory cells and a word line driver circuit for establishing a full power supply voltage on the word line. A bootstrapping circuit is coupled between the word line and a boost line for receiving a boost signal. The bootstrapping circuit includes a ferroelectric capacitor and coupling circuitry for coupling the ferroelectric capacitor between the boost line and the word line in a first operational mode such that the peak voltage on the word line is greater than the power supply voltage, and for isolating the ferroelectric capacitor from the boost line in a second operational mode. In operation, a selected word line is precharged to a full VDD power supply voltage, the ferroelectric capacitor associated with the selected word line is coupled to the boost line, the ferroelectric capacitors associated with non-selected word lines are electrically isolated from the boost line, and the boost line transitions from zero volts to VDD such that the voltage on the selected word line is boosted to a voltage greater than the VDD power supply voltage.

摘要翻译： 铁电存储器阵列包括耦合到一排铁电存储器单元的字线和用于在字线上建立全电源电压的字线驱动器电路。 自举电路耦合在字线和用于接收升压信号的升压线之间。 自举电路包括铁电电容器和耦合电路，其用于在第一操作模式下在升压线和字线之间耦合铁电电容器，使得字线上的峰值电压大于电源电压，并且用于隔离铁电 电容器从升压线在第二操作模式。 在操作中，选择的字线被预充电到一个完整的VDD电源电压，与所选字线相关联的铁电电容器耦合到升压线，与非选择的字线相关联的铁电电容器与升压线电隔离 ，并且升压线从零伏特转变为VDD，使得所选择的字线上的电压升高到大于VDD电源电压的电压。

公开(公告)号：US06266684B1

公开(公告)日：2001-07-24

申请号：US08907165

申请日：1997-08-06

申请人： William F. Kraus ,  Emily E. Clarke

发明人： William F. Kraus ,  Emily E. Clarke

IPC分类号： G06F1500

CPC分类号： G06F17/211 ,  G06F17/24

摘要： A web page authoring program allows a user to create a multiple frame web page by manipulating a graphical display representing the web page. The program presents a graphical display representing how the web page will appear when viewed through a web browser and allows the user to manipulate the graphical display directly to divide the web page into multiple frames. The program also allows the user to target a frame in the web page to display a particular web resource when the page is viewed through a web browser. In this regard, the program presents a graphical image representing the frameset structure of the web page and allows the user to target a frame by selecting a corresponding portion of the graphical image with a pointing device. In saving a portion of the web page, the program presents a miniature graphical image representing the structure of the web page and including a highlighted portion representing the portion of the web page to be saved and, in response to an instruction provided by the user, saves the portion of the web page in a storage medium.

摘要翻译： 网页创作程序允许用户通过操纵表示网页的图形显示来创建多帧网页。 该程序呈现图形显示，表示当通过网络浏览器查看时网页将如何显示，并允许用户直接操纵图形显示以将网页划分成多个帧。 该程序还允许用户在通过网络浏览器查看页面时，将网页中的一个框架定位以显示特定的网页资源。 在这方面，程序呈现表示网页的框架集结构的图形图像，并且允许用户通过用指示设备选择图形图像的相应部分来对准帧。 在保存网页的一部分时，该程序呈现表示网页结构的微型图形图像，并且包括表示要保存的网页的部分的突出显示部分，并且响应于用户提供的指令， 将网页的部分保存在存储介质中。