公开(公告)号：US07871897B2

公开(公告)日：2011-01-18

申请号：US12466178

申请日：2009-05-14

申请人： Dong-woon Shin ,  Soo-jin Hong ,  Guk-hyon Yon ,  Si-young Choi ,  Sun-ghil Lee

发明人： Dong-woon Shin ,  Soo-jin Hong ,  Guk-hyon Yon ,  Si-young Choi ,  Sun-ghil Lee

IPC分类号： H01L21/762

CPC分类号： H01L21/76229 ,  H01L21/823878 ,  H01L27/10894 ,  H01L27/11546

摘要： A mask pattern is formed on a semiconductor substrate in which a cell region, a PMOS region, and an NMOS region are defined. Trenches are formed in the cell region, the PMOS region, and the NMOS region. A sidewall oxide layer and a protection layer are formed in the trenches, and a portion of the protection layer in the PMOS region is removed. A first device isolation insulating layer is formed on the substrate, filling the trenches. Portions of the first device isolation insulating layer are removed to expose the mask pattern and the trenches of the cell region and the NMOS region and to leave a portion of the first device isolation insulating layer in the trench in the PMOS region. A liner is formed on the portion of the first device isolation region in the trench in the PMOS region and conforming to sidewalls of the trenches in the cell region and the NMOS region. A second device isolation insulating layer is formed on the substrate, filling the trenches in the cell region and the NMOS region. Portions of the second device isolation insulating layer are removed to expose the mask pattern and to leave portions of the second device isolation insulating layer in the trenches of the cell region and the NMOS region.

摘要翻译： 在其中限定了单元区域，PMOS区域和NMOS区域的半导体衬底上形成掩模图案。 在单元区域，PMOS区域和NMOS区域中形成沟槽。 在沟槽中形成侧壁氧化物层和保护层，并且去除PMOS区域中的保护层的一部分。 在衬底上形成第一器件隔离绝缘层，填充沟槽。 去除第一器件隔离绝缘层的部分以露出掩模图案和单元区域和NMOS区域的沟槽，并且在PMOS区域的沟槽中留下第一器件隔离绝缘层的一部分。 衬垫形成在PMOS区域的沟槽中的第一器件隔离区域的部分上，并且与衬底区域和NMOS区域中的沟槽的侧壁一致。 在衬底上形成第二器件隔离绝缘层，填充单元区域和NMOS区域中的沟槽。 去除第二器件隔离绝缘层的部分以暴露掩模图案并且将第二器件隔离绝缘层的部分留在单元区域和NMOS区域的沟槽中。

公开(公告)号：US20090311846A1

公开(公告)日：2009-12-17

申请号：US12466178

申请日：2009-05-14

申请人： Dong-Woon Shin ,  Soo-jin Hong ,  Guk-hyon Yon ,  Si-young Choi ,  Sun-ghil Lee

发明人： Dong-Woon Shin ,  Soo-jin Hong ,  Guk-hyon Yon ,  Si-young Choi ,  Sun-ghil Lee

IPC分类号： H01L21/762

CPC分类号： H01L21/76229 ,  H01L21/823878 ,  H01L27/10894 ,  H01L27/11546

摘要： A mask pattern is formed on a semiconductor substrate in which a cell region, a PMOS region, and an NMOS region are defined. Trenches are formed in the cell region, the PMOS region, and the NMOS region. A sidewall oxide layer and a protection layer are formed in the trenches, and a portion of the protection layer in the PMOS region is removed. A first device isolation insulating layer is formed on the substrate, filling the trenches. Portions of the first device isolation insulating layer are removed to expose the mask pattern and the trenches of the cell region and the NMOS region and to leave a portion of the first device isolation insulating layer in the trench in the PMOS region. A liner is formed on the portion of the first device isolation region in the trench in the PMOS region and conforming to sidewalls of the trenches in the cell region and the NMOS region. A second device isolation insulating layer is formed on the substrate, filling the trenches in the cell region and the NMOS region. Portions of the second device isolation insulating layer are removed to expose the mask pattern and to leave portions of the second device isolation insulating layer in the trenches of the cell region and the NMOS region.

摘要翻译： 在其中限定了单元区域，PMOS区域和NMOS区域的半导体衬底上形成掩模图案。 在单元区域，PMOS区域和NMOS区域中形成沟槽。 在沟槽中形成侧壁氧化物层和保护层，并且去除PMOS区域中的保护层的一部分。 在衬底上形成第一器件隔离绝缘层，填充沟槽。 去除第一器件隔离绝缘层的部分以露出掩模图案和单元区域和NMOS区域的沟槽，并且在PMOS区域的沟槽中留下第一器件隔离绝缘层的一部分。 衬垫形成在PMOS区域的沟槽中的第一器件隔离区域的部分上，并且与衬底区域和NMOS区域中的沟槽的侧壁一致。 在衬底上形成第二器件隔离绝缘层，填充单元区域和NMOS区域中的沟槽。 去除第二器件隔离绝缘层的部分以暴露掩模图案并且将第二器件隔离绝缘层的部分留在单元区域和NMOS区域的沟槽中。

公开(公告)号：US07807543B2

公开(公告)日：2010-10-05

申请号：US12134760

申请日：2008-06-06

申请人： Dong-woon Shin ,  Tai-su Park ,  Si-young Choi ,  Soo-jin Hong ,  Mi-jin Kim

发明人： Dong-woon Shin ,  Tai-su Park ,  Si-young Choi ,  Soo-jin Hong ,  Mi-jin Kim

IPC分类号： H01L21/76

CPC分类号： H01L21/823481 ,  H01L21/76229 ,  H01L21/823456 ,  H01L27/0921 ,  H01L27/105

摘要： A semiconductor device is manufactured by forming trenches in a substrate and selectively performing Plasma Ion Immersion Implantation and Deposition (PIIID) on a subset of the trenches in the substrate. The PIIID may be performed on only a portion of a surface of at least one of the trenches in the substrate. Semiconductor devices can include a semiconductor substrate having first, second and third trenches therein, and an oxide liner layer that fully lines the first trenches, that does not line the second trenches and that partially lines the third trenches.

摘要翻译： 通过在衬底中形成沟槽并且在衬底中的沟槽的子集上选择性地执行等离子体离子注入植入和沉积（PIIID）来制造半导体器件。 PIIID可以仅在衬底中的至少一个沟槽的表面的一部分上进行。 半导体器件可以包括其中具有第一，第二和第三沟槽的半导体衬底以及不对第一沟槽进行线条化的氧化物衬层，其不线性化第二沟槽并且部分地对第三沟槽进行排列。

公开(公告)号：US07785985B2

公开(公告)日：2010-08-31

申请号：US12133772

申请日：2008-06-05

申请人： Dong-woon Shin ,  Tai-su Park ,  Si-young Choi ,  Soo-jin Hong ,  Mi-jin Kim

发明人： Dong-woon Shin ,  Tai-su Park ,  Si-young Choi ,  Soo-jin Hong ,  Mi-jin Kim

IPC分类号： H01L21/76

CPC分类号： H01L21/823481 ,  H01L21/76229 ,  H01L21/823456 ,  H01L27/0921 ,  H01L27/105

摘要： Methods of manufacturing a semiconductor device, which can reduce hot electron induced punchthrough (HEIP) and/or improve the operating characteristics of the device include selectively forming an oxynitride layer in a device isolation layer according to the characteristics of transistors isolated by the device isolation layer. The methods include forming first trenches and second trenches on a substrate, forming an oxide layer on the surfaces of the first trenches and the second trenches, selectively forming an oxynitride layer on the second trenches by using plasma ion immersion implantation (PIII), and forming a buried insulating layer in the first trenches and the second trenches. The buried insulating layer may be planarized to form a first device isolation layer in the first trenches and a second device isolation layer in the second trenches.

摘要翻译： 可以减少热电子穿透（HEIP）和/或改善器件的工作特性的半导体器件的制造方法包括根据器件隔离层隔离的晶体管的特性选择性地在器件隔离层中形成氧氮化物层 。 所述方法包括在衬底上形成第一沟槽和第二沟槽，在第一沟槽和第二沟槽的表面上形成氧化物层，通过使用等离子体离子浸没注入（PIII）在第二沟槽上选择性地形成氧氮化物层，并形成 在第一沟槽和第二沟槽中的掩埋绝缘层。 掩埋绝缘层可以被平坦化以在第一沟槽中形成第一器件隔离层，在第二沟槽中形成第二器件隔离层。

公开(公告)号：US20090203188A1

公开(公告)日：2009-08-13

申请号：US12133772

申请日：2008-06-05

申请人： Dong-woon Shin ,  Tai-su Park ,  Si-young Choi ,  Soo-jin Hong ,  Mi-jin Kim

发明人： Dong-woon Shin ,  Tai-su Park ,  Si-young Choi ,  Soo-jin Hong ,  Mi-jin Kim

IPC分类号： H01L21/76

CPC分类号： H01L21/823481 ,  H01L21/76229 ,  H01L21/823456 ,  H01L27/0921 ,  H01L27/105

摘要： Methods of manufacturing a semiconductor device, which can reduce hot electron induced punchthrough (HEIP) and/or improve the operating characteristics of the device include selectively forming an oxynitride layer in a device isolation layer according to the characteristics of transistors isolated by the device isolation layer. The methods include forming first trenches and second trenches on a substrate, forming an oxide layer on the surfaces of the first trenches and the second trenches, selectively forming an oxynitride layer on the second trenches by using plasma ion immersion implantation (PIII), and forming a buried insulating layer in the first trenches and the second trenches. The buried insulating layer may be planarized to form a first device isolation layer in the first trenches and a second device isolation layer in the second trenches.

摘要翻译： 可以减少热电子穿透（HEIP）和/或改善器件的工作特性的半导体器件的制造方法包括根据器件隔离层隔离的晶体管的特性选择性地在器件隔离层中形成氧氮化物层 。 所述方法包括在衬底上形成第一沟槽和第二沟槽，在第一沟槽和第二沟槽的表面上形成氧化物层，通过使用等离子体离子浸没注入（PIII）在第二沟槽上选择性地形成氧氮化物层，并形成 在第一沟槽和第二沟槽中的掩埋绝缘层。 掩埋绝缘层可以被平坦化以在第一沟槽中形成第一器件隔离层，在第二沟槽中形成第二器件隔离层。

公开(公告)号：US08692372B2

公开(公告)日：2014-04-08

申请号：US12728396

申请日：2010-03-22

申请人： Dong-kak Lee ,  Sung-gil Kim ,  Soo-jin Hong ,  Sun-ghil Lee ,  Deok-hyung Lee

发明人： Dong-kak Lee ,  Sung-gil Kim ,  Soo-jin Hong ,  Sun-ghil Lee ,  Deok-hyung Lee

IPC分类号： H01L27/108 ,  H01L23/48 ,  H01L29/78

CPC分类号： H01L21/76843 ,  H01L21/28525 ,  H01L21/76847 ,  H01L21/76877 ,  H01L23/485 ,  H01L27/10855 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are semiconductor devices including a semiconductor substrate, an insulating layer including a contact hole through which the semiconductor substrate is exposed, and a polysilicon layer filling the contact hole. The polysilicon layer is doped with impurities and includes an impurity-diffusion prevention layer. In the semiconductor devices, the impurities included in the polysilicon layer do not diffuse into the insulating layer and the semiconductor substrate due to the impurity-diffusion prevention layers.

摘要翻译： 提供了包括半导体衬底，包括暴露半导体衬底的接触孔的绝缘层和填充接触孔的多晶硅层的半导体器件。 多晶硅层掺杂有杂质，并且包括杂质扩散防止层。 在半导体器件中，包含在多晶硅层中的杂质不会由于杂质扩散层而扩散到绝缘层和半导体衬底中。

公开(公告)号：US20110049596A1

公开(公告)日：2011-03-03

申请号：US12728396

申请日：2010-03-22

申请人： Dong-kak Lee ,  Sung-gil Kim ,  Soo-jin Hong ,  Sun-ghil Lee ,  Deok-hyung Lee

发明人： Dong-kak Lee ,  Sung-gil Kim ,  Soo-jin Hong ,  Sun-ghil Lee ,  Deok-hyung Lee

IPC分类号： H01L27/108 ,  H01L23/48 ,  H01L29/78

CPC分类号： H01L21/76843 ,  H01L21/28525 ,  H01L21/76847 ,  H01L21/76877 ,  H01L23/485 ,  H01L27/10855 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are semiconductor devices including a semiconductor substrate, an insulating layer including a contact hole through which the semiconductor substrate is exposed, and a polysilicon layer filling the contact hole. The polysilicon layer is doped with impurities and includes an impurity-diffusion prevention layer. In the semiconductor devices, the impurities included in the polysilicon layer do not diffuse into the insulating layer and the semiconductor substrate due to the impurity-diffusion prevention layers.

摘要翻译： 提供了包括半导体衬底，包括暴露半导体衬底的接触孔的绝缘层和填充接触孔的多晶硅层的半导体器件。 多晶硅层掺杂有杂质，并且包括杂质扩散防止层。 在半导体器件中，包含在多晶硅层中的杂质不会由于杂质扩散层而扩散到绝缘层和半导体衬底中。

公开(公告)号：US5677232A

公开(公告)日：1997-10-14

申请号：US754889

申请日：1996-11-22

申请人： Sung-eui Kim ,  Soo-jin Hong

发明人： Sung-eui Kim ,  Soo-jin Hong

IPC分类号： H01L21/316 ,  H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76202 ,  H01L21/76229 ,  H01L21/76235

摘要： An isolation region is formed on a substrate by forming spaced apart mesas on the substrate. A first insulation region is then formed on the substrate and second insulation regions are formed on the mesas, the first insulation region being disposed between and spaced apart from a respective one of the mesas, a respective one of the second insulation regions capping a respective one of the mesas. Preferably, the first and second insulation regions are formed by forming sidewall spacers adjacent sidewall portions of the mesas and oxidizing portions of the mesas opposite the substrate and a portion of the substrate disposed between the sidewall spacers. Spaced apart trenches are formed in the substrate on opposite sides of the first insulation region, a respective one of the trenches being disposed between the first insulation region and a respective one of the mesas, preferably by removing the sidewall spacers and underlying portions of the substrate. An insulating layer is formed on the substrate, filling the trenches and covering the first insulation region, and the substrate is planarized to remove portions of the insulating layer and the second insulation regions and thereby expose underlying portions of the mesas and leave a third insulation region spanning the trenches.

摘要翻译： 通过在衬底上形成间隔开的台面，在衬底上形成隔离区。 然后在基板上形成第一绝缘区域，并且在台面上形成第二绝缘区域，第一绝缘区域设置在相应的一个台面之间并与相应的一个台面间隔开，第一绝缘区域中的相应一个覆盖相应的一个 的台面。 优选地，第一和第二绝缘区域通过形成邻近台面的侧壁部分的侧壁间隔和与衬底相对的台面的氧化部分和设置在侧壁间隔件之间的衬底的一部分而形成。 隔开的沟槽在第一绝缘区域的相对侧上的衬底中形成，相应的沟槽设置在第一绝缘区域和相应的台面之间，优选地通过去除侧壁间隔件和衬底的下面部分 。 在衬底上形成绝缘层，填充沟槽并覆盖第一绝缘区域，并且将衬底平坦化以去除绝缘层和第二绝缘区域的部分，从而暴露台面的下面部分并留下第三绝缘区域 跨越壕沟

公开(公告)号：US06624041B2

公开(公告)日：2003-09-23

申请号：US09316029

申请日：1999-05-21

申请人： Soo-jin Hong ,  Moon-han Park

发明人： Soo-jin Hong ,  Moon-han Park

IPC分类号： H01L2176

CPC分类号： H01L21/76224 ,  H01L21/823481

摘要： A method for forming a trench type isolation film comprises filling a trench with a composite film, flattening the resultant, and annealing the flattened resultant before a gate oxide film is formed. The annealing diffuses out any contaminant existing in an area near and/or contacting the trench on a surface between a semiconductor substrate and a pad oxide film. Therefore, it is possible to prevent the portion of the gate oxide film which is near the trench from becoming thinner than other portions. Accordingly, it is possible to prevent the characteristic of the gate oxide film from deteriorating. In particular, it is possible to prevent a break down voltage from being lowered.

摘要翻译： 用于形成沟槽型隔离膜的方法包括用复合膜填充沟槽，使所得的产品平坦化，并且在形成栅极氧化膜之前使扁平化的结果退火。 退火在半导体衬底和衬垫氧化物膜之间的表面上扩散存在于接近和/或接触沟槽的区域中的任何污染物。 因此，可以防止沟槽附近的栅极氧化膜的部分变得比其他部分薄。 因此，可以防止栅极氧化膜的特性劣化。 特别地，可以防止分解电压降低。

公开(公告)号：US6121110A

公开(公告)日：2000-09-19

申请号：US124093

申请日：1998-07-29

申请人： Soo-jin Hong ,  Yu-gyun Shin ,  Han-sin Lee ,  Hyun-cheol Choe

发明人： Soo-jin Hong ,  Yu-gyun Shin ,  Han-sin Lee ,  Hyun-cheol Choe

IPC分类号： H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76224

摘要： A trench isolation method is provided. In the trench isolation method, a pad oxide film, an oxidative film and an etching mask film are formed on a semiconductor substrate in sequence, and then a trench is formed in a field region of the semiconductor substrate. A oxide film is formed at the inner wall of the trench and the side walls of the oxidative film by oxidizing the semiconductor substrate. After filling the trench with a dielectric material, the pad oxide film, oxidative film and etching mask film formed in the active region are removed.

摘要翻译： 提供沟槽隔离方法。 在沟槽隔离方法中，顺序地在半导体衬底上形成衬垫氧化膜，氧化膜和蚀刻掩模膜，然后在半导体衬底的场区域中形成沟槽。 通过氧化半导体衬底，在沟槽的内壁和氧化膜的侧壁上形成氧化膜。 在用电介质材料填充沟槽之后，去除在活性区域中形成的衬垫氧化膜，氧化膜和蚀刻掩模膜。