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    Trench isolation method for semiconductor device
    1.
    发明授权
    Trench isolation method for semiconductor device 失效
    半导体器件的沟槽隔离方法

    公开(公告)号：US6121110A

    公开(公告)日：2000-09-19

    申请号：US124093

    申请日：1998-07-29

    申请人： Soo-jin Hong ,  Yu-gyun Shin ,  Han-sin Lee ,  Hyun-cheol Choe

    发明人： Soo-jin Hong ,  Yu-gyun Shin ,  Han-sin Lee ,  Hyun-cheol Choe

    IPC分类号： H01L21/76 ,  H01L21/762

    CPC分类号： H01L21/76224

    摘要： A trench isolation method is provided. In the trench isolation method, a pad oxide film, an oxidative film and an etching mask film are formed on a semiconductor substrate in sequence, and then a trench is formed in a field region of the semiconductor substrate. A oxide film is formed at the inner wall of the trench and the side walls of the oxidative film by oxidizing the semiconductor substrate. After filling the trench with a dielectric material, the pad oxide film, oxidative film and etching mask film formed in the active region are removed.

    摘要翻译： 提供沟槽隔离方法。 在沟槽隔离方法中，顺序地在半导体衬底上形成衬垫氧化膜，氧化膜和蚀刻掩模膜，然后在半导体衬底的场区域中形成沟槽。 通过氧化半导体衬底，在沟槽的内壁和氧化膜的侧壁上形成氧化膜。 在用电介质材料填充沟槽之后，去除在活性区域中形成的衬垫氧化膜，氧化膜和蚀刻掩模膜。

    Annealing methods for forming isolation trenches
    2.
    发明授权
    Annealing methods for forming isolation trenches 失效
    用于形成隔离沟的退火方法

    公开(公告)号：US5858858A

    公开(公告)日：1999-01-12

    申请号：US729453

    申请日：1996-10-11

    申请人： Tai-su Park ,  Moon-han Park ,  Yu-gyun Shin ,  Han-sin Lee

    发明人： Tai-su Park ,  Moon-han Park ,  Yu-gyun Shin ,  Han-sin Lee

    IPC分类号： H01L21/76 ,  H01L21/762

    CPC分类号： H01L21/76224

    摘要： A method for forming a microelectronic structure includes the steps of forming a mask layer on a substrate, forming a trench in the exposed portion of the substrate, forming a layer of an insulating material which fills the trench and covers the mask layer, and annealing the insulating material at a temperature of at least about 1,150.degree. C. The annealing step can be performed for a period of time of about .5 hours to about 8 hours, and the annealing step can be performed in an inert atmosphere.

    摘要翻译： 一种形成微电子结构的方法包括以下步骤：在衬底上形成掩模层，在衬底的暴露部分形成沟槽，形成填充沟槽并覆盖掩模层的绝缘材料层，并退火 绝缘材料在至少约1150℃的温度下进行。退火步骤可以进行约0.5小时至约8小时的时间，退火步骤可以在惰性气氛中进行。

    Method of forming isolation film for semiconductor devices
    3.
    发明授权
    Method of forming isolation film for semiconductor devices 失效
    形成半导体器件隔离膜的方法

    公开(公告)号：US06258726B1

    公开(公告)日：2001-07-10

    申请号：US09412888

    申请日：1999-10-05

    申请人： Tai-Su Park ,  Yu-gyun Shin ,  Han-sin Lee ,  Kyung-won Park

    发明人： Tai-Su Park ,  Yu-gyun Shin ,  Han-sin Lee ,  Kyung-won Park

    IPC分类号： H01L21302

    CPC分类号： H01L21/76224

    摘要： A method of forming an isolation film forms a spacer for connecting the edge of an active region to the isolation film. The spacer is on the upper sidewall of a trench and smoothes the transition or step between the level of the isolation film and the level of the active region. Accordingly, a gate oxide film of a uniform thickness can be formed on the entire active region in a subsequent process, thus preventing degradation of the characteristics of the gate oxide film. The spacer can be formed using a sidewall spacer on the hard mask used for forming the trench. The sidewall spacer protects part of the isolation formed in the trench, and etching after removal of the sidewall spacer can round the protected portion to create the spacer. Furthermore, to dispel stresses and defects in the isolation film, annealing for densification of the isolation film can be performed at a high temperature such as about 1150° C. because the spacer mitigates the effects of shrinking or sagging of the isolation film.

    摘要翻译： 形成隔离膜的方法形成用于将有源区域的边缘连接到隔离膜的间隔物。 间隔物位于沟槽的上侧壁上，并平滑了隔离膜的电平与有源区的电平之间的转变或台阶。 因此，可以在随后的工艺中在整个有源区上形成均匀厚度的栅极氧化膜，从而防止栅极氧化膜的特性劣化。 间隔物可以使用用于形成沟槽的硬掩模上的侧壁间隔物形成。 侧壁间隔件保护形成在沟槽中的隔离部分，并且在去除侧壁间隔物之后的蚀刻可围绕被保护部分以形成隔离物。 此外，为了消除隔离膜中的应力和缺陷，隔离膜的致密化退火可以在诸如约1150℃的高温下进行，因为间隔物减轻了隔离膜的收缩或下垂的影响。

    Device isolation method of semiconductor device
    5.
    发明授权
    Device isolation method of semiconductor device 失效
    半导体器件的器件隔离方法

    公开(公告)号：US5641705A

    公开(公告)日：1997-06-24

    申请号：US470914

    申请日：1995-06-06

    申请人： Dong-ho Ahn ,  Seong-joon Ahn ,  Yu-gyun Shin ,  Yun-gi Kim

    发明人： Dong-ho Ahn ,  Seong-joon Ahn ,  Yu-gyun Shin ,  Yun-gi Kim

    IPC分类号： H01L21/316 ,  H01L21/32 ,  H01L21/76 ,  H01L21/762

    CPC分类号： H01L21/76205 ,  H01L21/32

    摘要： In a device isolation method for a semiconductor device, after a pad oxide layer and a nitride layer are formed on a semiconductor substrate, the nitride layer located above the device isolation region is removed. An undercut is formed under the nitride by partially etching the pad oxide layer. After a first oxide layer is formed on the exposed substrate and a polysilicon spacer is formed on the sidewalls of the nitride layer, a void is formed in the oxide layer under the nitride layer which is formed on the active region by oxidizing the resultant structure in which the polysilicon spacer is formed at a temperature above 950.degree. C. Thus, good cell definition and stable device isolation can be realized, while solving the typical problem of conventional LOCOS methods by forming the void intentionally in the pad oxide layer thickened by bird's beak punch through.

    摘要翻译： 在半导体器件的器件隔离方法中，在衬底氧化物层和氮化物层形成在半导体衬底上之后，去除位于器件隔离区上方的氮化物层。 通过部分蚀刻衬垫氧化物层，在氮化物之下形成底切。 在暴露的基板上形成第一氧化物层并在氮化物层的侧壁上形成多晶硅间隔物之后，在形成于有源区上的氮化物层下面的氧化物层中形成空穴， 其中多晶硅间隔物在高于950℃的温度下形成。因此，通过在通过鸟喙加厚的垫氧化物层中有意地形成空穴来解决常规LOCOS方法的典型问题，可以实现良好的电池定义和稳定的器件隔离 穿透

    Method of Manufacturing Semiconductor Device Having Stress Creating Layer
    7.
    发明申请
    Method of Manufacturing Semiconductor Device Having Stress Creating Layer 有权
    制造具有应力创造层的半导体器件的方法

    公开(公告)号：US20100197092A1

    公开(公告)日：2010-08-05

    申请号：US12693080

    申请日：2010-01-25

    申请人： Jin-bum Kim ,  Wook-je Kim ,  Yu-gyun Shin ,  Kwan-heum Lee ,  Sun-Ghil Lee

    发明人： Jin-bum Kim ,  Wook-je Kim ,  Yu-gyun Shin ,  Kwan-heum Lee ,  Sun-Ghil Lee

    IPC分类号： H01L21/8238 ,  H01L21/20

    CPC分类号： H01L29/7848 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636

    摘要： Provided is a simplified method of manufacturing a semiconductor device having a stress creating layer. A first conductive first impurity region is formed on a semiconductor substrate on both sides of a first gate of a first area of the semiconductor substrate, and a second conductive second impurity region is formed on the semiconductor substrate on both sides of a second gate of a second area. First and second spacers are formed on sidewalls of the first and second gates, respectively. First and second semiconductor layers are formed in portions of the semiconductor substrate so as to contact the first and second impurity regions, respectively. The second semiconductor layer is removed. First and second barrier layers are formed in the first and second contact holes of the insulation layer, respectively.

    摘要翻译： 提供了一种制造具有应力产生层的半导体器件的简化方法。 在半导体衬底的第一区域的第一栅极的两侧上的半导体衬底上形成第一导电第一杂质区，并且在半导体衬底的第二栅极的两侧的半导体衬底上形成第二导电第二杂质区 第二区。 第一和第二间隔物分别形成在第一和第二栅极的侧壁上。 第一半导体层和第二半导体层分别形成在半导体衬底的部分中，以分别接触第一和第二杂质区。 去除第二半导体层。 第一和第二阻挡层分别形成在绝缘层的第一和第二接触孔中。

    High dielectric film and related method of manufacture
    8.
    发明授权
    High dielectric film and related method of manufacture 有权
    高介电膜及相关制造方法

    公开(公告)号：US07521331B2

    公开(公告)日：2009-04-21

    申请号：US11359404

    申请日：2006-02-23

    申请人： Hong-bae Park ,  Yu-gyun Shin ,  Sang-bom Kang

    发明人： Hong-bae Park ,  Yu-gyun Shin ,  Sang-bom Kang

    IPC分类号： H01L21/76

    CPC分类号： H01L21/0228 ,  C23C16/308 ,  C23C16/45531 ,  H01L21/02142 ,  H01L21/02194 ,  H01L21/02274 ,  H01L21/3141 ,  H01L21/3145 ,  H01L21/31645

    摘要： A method of forming a high dielectric film for a semiconductor device comprises supplying a first source gas to a reaction chamber during a first time interval, supplying a first reactant gas to the reaction chamber during a second time interval after the first time interval, supplying a second source gas to the reaction chamber for a third time interval after the second time interval, supplying a second reactant gas to the reaction chamber for a fourth time interval after the third time interval, and supplying an additive gas including nitrogen to the reaction chamber during a fifth time interval.

    摘要翻译： 形成用于半导体器件的高电介质膜的方法包括：在第一时间间隔内将第一源气体供应到反应室，在第一时间间隔之后的第二时间间隔期间将第一反应气体供应到反应室， 在所述第二时间间隔之后的第三时间间隔内将第二源气体供应到所述反应室，在所述第三时间间隔之后，将第二反应气体供应到所述反应室中第四时间间隔，并且在所述第三时间间隔内向所述反应室供应包含氮气的添加剂气体 第五个时间间隔。

    Isolation method of semiconductor device using second pad oxide layer formed through chemical vapor deposition (CVD)
    10.
    发明授权
    Isolation method of semiconductor device using second pad oxide layer formed through chemical vapor deposition (CVD) 失效
    使用通过化学气相沉积（CVD）形成的第二衬垫氧化物层的半导体器件的隔离方法

    公开(公告)号：US6093622A

    公开(公告)日：2000-07-25

    申请号：US148060

    申请日：1998-09-04

    申请人： Dong-ho Ahn ,  Sung-eui Kim ,  Yu-gyun Shin

    发明人： Dong-ho Ahn ,  Sung-eui Kim ,  Yu-gyun Shin

    IPC分类号： H01L21/285 ,  H01L21/316 ,  H01L21/76 ,  H01L21/762

    CPC分类号： H01L21/76202

    摘要： An isolation method in the fabrication process of a semiconductor device is provided. The method forms an oxide layer as a buffer layer for reducing stress through chemical vapor deposition (CVD). By the method, a first pad oxide layer and a silicon nitride layer are formed on a semiconductor substrate, and then an silicon nitride layer pattern is formed by patterning, and undercuts are formed in the first pad oxide layer pattern. Subsequently, a second pad oxide layer is formed on the entire surface of the semiconductor substrate through CVD, and then spacers are formed on the sidewalls of both the patterned first pad oxide layer and silicon nitride layer and a field oxide layer is formed through thermal oxidation. Alternatively, a silicon layer is deposited without the spacers to form the field oxide layer. The second pad oxide layer is a buffer layer for buffering stress during formation of the field oxide layer.

    摘要翻译： 提供了半导体器件的制造工艺中的隔离方法。 该方法形成通过化学气相沉积（CVD）来减少应力的缓冲层的氧化物层。 通过该方法，在半导体衬底上形成第一衬垫氧化物层和氮化硅层，然后通过图案形成氮化硅层图案，并且在第一衬垫氧化物层图案中形成底切。 随后，通过CVD在半导体衬底的整个表面上形成第二焊盘氧化物层，然后在图案化的第一焊盘氧化物层和氮化硅层的侧壁上形成间隔物，并且通过热氧化形成场氧化物层 。 或者，沉积硅层而没有间隔物以形成场氧化物层。 第二衬垫氧化物层是用于在形成场氧化物层期间缓冲应力的缓冲层。