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42 条记录 (耗时 0.027 秒)

    Structure and method for hyper-abrupt junction varactors
    2.
    发明授权
    Structure and method for hyper-abrupt junction varactors 有权
    超突变连接变容二极管的结构和方法

    公开(公告)号：US07253073B2

    公开(公告)日：2007-08-07

    申请号：US10707905

    申请日：2004-01-23

    申请人： Douglas D. Coolbaugh ,  Stephen S. Furkay ,  Jeffrey B. Johnson ,  Robert M. Rassel ,  David C. Sheridan

    发明人： Douglas D. Coolbaugh ,  Stephen S. Furkay ,  Jeffrey B. Johnson ,  Robert M. Rassel ,  David C. Sheridan

    IPC分类号： H01L21/20 ,  H01L21/8234 ,  H01L21/425

    CPC分类号： H01L29/93 ,  H01L29/94

    摘要： A method and device providing a HA junction varactor which may be fabricated with a reduced variation in C-V tuning curve from one varactor to the next. The process produces a varactor with an active region formed substantially by doping an Si substrate with various dopants at various energy levels. Accordingly, unit-to-unit device variation is reduced because etching, growing, and deposition processes to make the active portion of the varactor are reduced or eliminated. The resulting HA junction has a more uniform thickness, and a more uniform doping profile.

    摘要翻译： 提供HA结变容二极管的方法和装置，其可以以从一个变容二极管到下一个变容二极管的C-V调谐曲线的变化减小来制造。 该方法产生可变电抗器，其中有源区基本上通过以各种能级掺杂各种掺杂剂的Si衬底而形成。 因此，由于蚀刻，生长和沉积工艺以使变容二极管的活性部分减少或消除，因此减小了单元到单元的装置变化。 所得到的HA结具有更均匀的厚度和更均匀的掺杂分布。

    Structure and method of hyper-abrupt junction varactors
    3.
    发明授权
    Structure and method of hyper-abrupt junction varactors 有权
    超突变结可变电抗器的结构和方法

    公开(公告)号：US07183628B2

    公开(公告)日：2007-02-27

    申请号：US11004877

    申请日：2004-12-07

    申请人： Douglas D. Coolbaugh ,  Stephen S. Furkay ,  Jeffrey B. Johnson ,  Robert M. Rassel ,  David C. Sheridan

    发明人： Douglas D. Coolbaugh ,  Stephen S. Furkay ,  Jeffrey B. Johnson ,  Robert M. Rassel ,  David C. Sheridan

    IPC分类号： H01L29/93

    CPC分类号： H01L29/93 ,  H01L29/94

    摘要： A method and device providing a HA junction varactor which may be fabricated with a reduced variation in C-V tuning curve from one varactor to the next. The process produces a varactor with an active region formed substantially by doping an Si substrate with various dopants at various energy levels. Accordingly, unit-to-unit device variation is reduced because etching, growing, and deposition processes to make the active portion of the varactor are reduced or eliminated. The resulting HA junction has a more uniform thickness, and a more uniform doping profile.

    摘要翻译： 提供HA结变容二极管的方法和装置，其可以以从一个变容二极管到下一个变容二极管的C-V调谐曲线的变化减小来制造。 该方法产生可变电抗器，其中有源区基本上通过以各种能级掺杂各种掺杂剂的Si衬底而形成。 因此，由于蚀刻，生长和沉积工艺以使变容二极管的活性部分减少或消除，因此减小了单元到单元的装置变化。 所得到的HA结具有更均匀的厚度和更均匀的掺杂分布。

    Design structure with a deep sub-collector, a reach-through structure and trench isolation
    8.
    发明授权
    Design structure with a deep sub-collector, a reach-through structure and trench isolation 有权
    具有深子集电极的设计结构，通孔结构和沟槽隔离

    公开(公告)号：US08015538B2

    公开(公告)日：2011-09-06

    申请号：US11941104

    申请日：2007-11-16

    申请人： Douglas D Coolbaugh ,  Xuefeng Liu ,  Robert M. Rassel ,  David C. Sheridan ,  Steven H. Voldman

    发明人： Douglas D Coolbaugh ,  Xuefeng Liu ,  Robert M. Rassel ,  David C. Sheridan ,  Steven H. Voldman

    IPC分类号： G06F17/50 ,  G06F11/22 ,  G06F9/455 ,  H01L29/00 ,  H01L21/8238 ,  H01L21/20

    CPC分类号： H01L29/0821 ,  H01L29/66272

    摘要： The invention relates to noise isolation in semiconductor devices, and a design structure on which a subject circuit resides. A design structure is embodied in a machine readable medium used in a design process. The design structure includes a deep sub-collector located in a first epitaxial layer, and a doped region located in a second epitaxial layer, which is above the first epitaxial layer. The design structure further includes a reach-through structure penetrating from a surface of the device through the first and second epitaxial layers to the deep sub-collector, and a trench isolation structure penetrating from a surface of the device and surrounding the doped region.

    摘要翻译： 本发明涉及半导体器件中的噪声隔离以及被摄体电路所在的设计结构。 设计结构体现在在设计过程中使用的机器可读介质中。 该设计结构包括位于第一外延层中的深子集电极和位于第一外延层之上的第二外延层中的掺杂区域。 该设计结构进一步包括从装置的表面穿过第一外延层和第二外延层到达深亚集电体的通孔结构，以及从该器件的表面穿透且围绕掺杂区域的沟槽隔离结构。

    Buried subcollector for high frequency passive semiconductor devices
    9.
    发明授权
    Buried subcollector for high frequency passive semiconductor devices 失效
    埋地子集电极用于高频无源半导体器件

    公开(公告)号：US07491632B2

    公开(公告)日：2009-02-17

    申请号：US11164108

    申请日：2005-11-10

    申请人： Douglas D. Coolbaugh ,  Xuefeng Liu ,  Robert M. Rassel ,  David C. Sheridan

    发明人： Douglas D. Coolbaugh ,  Xuefeng Liu ,  Robert M. Rassel ,  David C. Sheridan

    IPC分类号： H01L21/425

    CPC分类号： H01L21/8249 ,  H01L29/0821 ,  H01L29/66272

    摘要： A method of fabricating a buried subcollector in which the buried subcollector is implanted to a depth in which during subsequent epi growth the buried subcollector remains substantially below the fictitious interface between the epi layer and the substrate is provided. In particular, the inventive method forms a buried subcollector having an upper surface (i.e., junction) that is located at a depth from about 3000 Å or greater from the upper surface of the semiconductor substrate. This deep buried subcollector having an upper surface that is located at a depth from about 3000 Å or greater from the upper surface of the substrate is formed using a reduced implant energy (as compared to a standard deep implanted subcollector process) at a relative high dose. The present invention also provides a semiconductor structure including the inventive buried subcollector which can be used as cathode for passive devices in high frequency applications.

    摘要翻译： 一种制造掩埋子集电极的方法，其中将埋入的子集电极注入深度，其中在随后的外延生长期间，掩埋子集电极基本上保持在外延层和衬底之间的虚拟界面的下方。 特别地，本发明的方法形成了具有从半导体衬底的上表面位于距离大约或更大的深度的上表面（即结）的掩埋子集电极。 该深埋底部集电器具有从衬底的上表面位于距离大约等于或更大的深度的上表面，其使用相对高剂量的减少的注入能量（与标准深度植入子集电极过程相比） 。 本发明还提供了一种半导体结构，其包括本发明的掩埋子集电极，其可以用作高频应用中的无源器件的阴极。