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公开(公告)号：US06956518B1
公开(公告)日：2005-10-18
申请号：US10816564
申请日：2004-03-31
申请人： Douglas Piasecki , Ka Y. Leung , Kenneth Fernald
发明人： Douglas Piasecki , Ka Y. Leung , Kenneth Fernald
摘要： Method and apparatus for subclocking a SAR analog-to-digital converter. A method is disclosed for clocking the operation of a SAR analog-to-digital converter (ADC). A low frequency clock and a high frequency clock are provided. An analog input voltage is then tracked during a tracking phase to sample the value thereof. A conversion cycle referenced to an edge of the low frequency clock is then initiated. The sampled data is then converted in a conversion operation during a data conversion cycle, which conversion operation requires a plurality of conversion clock cycles, the timing of at least a portion of the conversion operation is controlled during the data conversion cycle utilizing the high frequency clock as the conversion clock.
摘要翻译： SAR模数转换器的次频方法和装置。 公开了一种用于计时SAR模数转换器（ADC）的操作的方法。 提供了低频时钟和高频时钟。 然后在跟踪阶段跟踪模拟输入电压以对其值进行采样。 然后启动参考低频时钟边沿的转换周期。 然后，在数据转换周期期间，在转换操作中转换采样数据，该转换操作需要多个转换时钟周期，在利用高频时钟的数据转换周期期间控制转换操作的至少一部分的定时 作为转换时钟。
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公开(公告)号：US06922164B1
公开(公告)日：2005-07-26
申请号：US10815416
申请日：2004-03-31
CPC分类号： H03M1/462
摘要： SAR analog-to-digital converter with abort function. A method for increasing the throughput of a data converter decision is disclosed. First, a data conversion operation is initiated to convert analog signals on an analog input on a data converter to digital data by sampling the analog signals on the analog signal input and then converting the sampled analog signals to digital data with a predetermined data conversion algorithm in a data conversion operation. The digital output of the data converter is compared to a threshold voltage value. When the output of the data converter is determined by the step of comparing to meet a predetermined relationship relative to the threshold voltage, the data conversion operation is terminated prior to the complete execution of the data conversion operation on the sampled analog signals.
摘要翻译： 具有中止功能的SAR模数转换器。 公开了一种用于增加数据转换器决定的吞吐量的方法。 首先，通过对模拟信号输入上的模拟信号进行采样，然后利用预定的数据转换算法将采样的模拟信号转换成数字数据，开始数据转换操作以将数据转换器上的模拟输入上的模拟信号转换成数字数据 数据转换操作。 将数据转换器的数字输出与阈值电压值进行比较。 当通过比较步骤确定数据转换器的输出以达到相对于阈值电压的预定关系时，在对采样的模拟信号完成数据转换操作之后终止数据转换操作。
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公开(公告)号：US06950044B1
公开(公告)日：2005-09-27
申请号：US10816262
申请日：2004-03-31
申请人： Douglas Piasecki , Ka Y. Leung
发明人： Douglas Piasecki , Ka Y. Leung
CPC分类号： H03M1/0872
摘要： Mixed signal processor with noise management. A method for noise management in a mixed signal processor integrated circuit having a digital processing section and an analog section The digital processing section is clocked at a first clock rate to process digital data. When a conversion operation is to be carried out by the analog section, the clocking of the digital processing section is inhibited during at least a portion of the data conversion operation by the analog section to prevent noise from clock transitions in the digital processing section from being injected into the analog section during the at least a portion of th data conversion operation.
摘要翻译： 具有噪声管理的混合信号处理器。 一种具有数字处理部分和模拟部分的混合信号处理器集成电路中的噪声管理方法数字处理部分以第一时钟速率被计时以处理数字数据。 当要由模拟部分执行转换操作时，数字处理部分的时钟在模拟部分的数据转换操作的至少一部分期间被禁止，以防止数字处理部分中的时钟转换的噪声成为 在数据转换操作的至少一部分期间注入模拟部分。
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4.发明授权Method and apparatus for combining outputs of multiple DACs for increased bit resolution 有权用于组合多个DAC的输出以提高比特分辨率的方法和装置公开(公告)号：US06950047B1
公开(公告)日：2005-09-27
申请号：US10816436
申请日：2004-03-31
摘要： Method and apparatus for combining outputs of multiple DACs for increased bit resolution. A method for providing an increased bit resolution to a data converter operable to convert digital information to analog values. A first current Digital-to-Analog (IDAC) converter is controlled to provide current to a first output node, the first IDAC having a first current step size associated with the Least Significant Bit (LSB) thereof. A second IDAC is controlled to provide current to the first output node, the second IDAC having a second current step size associated with the LSB thereof that is smaller than the first current step size. The combination of the first and second IDACs increases the bit resolution of the first IDAC when driving the first output node with the second IDAC.
摘要翻译： 用于组合多个DAC的输出以提高比特分辨率的方法和装置。 一种用于向可操作以将数字信息转换为模拟值的数据转换器提供增加的位分辨率的方法。 控制第一当前数模（IAC）转换器以向第一输出节点提供电流，第一IDAC具有与其最低有效位（LSB）相关联的第一当前步长。 控制第二IDAC以向第一输出节点提供电流，第二IDAC具有与其LSB的相关联的小于第一当前步长的第二当前步长。 当用第二IDAC驱动第一输出节点时，第一和第二IDAC的组合增加了第一IDAC的位分辨率。
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公开(公告)号：US20060212679A1
公开(公告)日：2006-09-21
申请号：US11381707
申请日：2006-05-04
申请人： Donald Alfano , Danny Allred , Douglas Piasecki , Kenneth Fernald , Ka Leung , Brian Caloway , Alvin Storvik , Paul Highley , Douglas Holberg
发明人： Donald Alfano , Danny Allred , Douglas Piasecki , Kenneth Fernald , Ka Leung , Brian Caloway , Alvin Storvik , Paul Highley , Douglas Holberg
IPC分类号： G06F15/00
CPC分类号： G06F13/385 , G06F1/08 , G06F15/7814 , H03M1/122 , H03M1/183 , H03M1/462 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Field programmable mixed-signal integrated circuit. A reconfigurable processor system includes a processor core is provided that operates on a set of instructions to carry out predefined processes. A plurality of input/output pins are provided for interfacing with external signals. A reconfigurable interface interfaces between the processor core and the input/output pins. The reconfigurable interface is operable to define how each of the plurality of input/output pins interfaces with the processor core and the functionality associated therewith.
摘要翻译： 现场可编程混合信号集成电路。 可重新配置的处理器系统包括提供处理器核心，其操作一组指令以执行预定义的过程。 提供多个输入/输出引脚用于与外部信号进行接口。 处理器核心和输入/输出引脚之间的可重配置接口接口。 可重构接口可操作以定义多个输入/输出引脚中的每一个如何与处理器核心和与其相关联的功能。
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6.发明申请公开(公告)号：US20050219108A1
公开(公告)日：2005-10-06
申请号：US10816564
申请日：2004-03-31
申请人： Douglas Piasecki , Ka Leung , Kenneth Fernald
发明人： Douglas Piasecki , Ka Leung , Kenneth Fernald
摘要： Method and apparatus for subclocking a SAR analog-to-digital converter. A method is disclosed for clocking the operation of a SAR analog-to-digital converter (ADC). A low frequency clock and a high frequency clock are provided. An analog input voltage is then tracked during a tracking phase to sample the value thereof. A conversion cycle referenced to an edge of the low frequency clock is then initiated. The sampled data is then converted in a conversion operation during a data conversion cycle, which conversion operation requires a plurality of conversion clock cycles. The timing of at least a portion of the conversion operation is controlled during the data conversion cycle utilizing the high frequency clock as the conversion clock.
摘要翻译： SAR模数转换器的次频方法和装置。 公开了一种用于计时SAR模数转换器（ADC）的操作的方法。 提供了低频时钟和高频时钟。 然后在跟踪阶段跟踪模拟输入电压以对其值进行采样。 然后启动参考低频时钟边沿的转换周期。 然后在数据转换周期期间，在转换操作中转换采样数据，该转换操作需要多个转换时钟周期。 在利用高频时钟作为转换时钟的数据转换周期期间，控制转换操作的至少一部分的定时。
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7.发明申请METHOD AND APPARATUS FOR COMBINING OUTPUTS OF MULTIPLE DACS FOR INCREASED BIT RESOLUTION 有权用于组合多个DAC的输出用于增加的分辨率的方法和装置公开(公告)号：US20050219093A1
公开(公告)日：2005-10-06
申请号：US10816436
申请日：2004-03-31
摘要： Method and apparatus for combining outputs of multiple DACs for increased bit resolution. A method for providing an increased bit resolution to a data converter operable to convert digital information to analog values. A first current Digital-to-Analog (IDAC) converter is controlled to provide current to a first output node, the first IDAC having a first current step size associated with the Least Significant Bit (LSB) thereof. A second IDAC is controlled to provide current to the first output node, the second IDAC having a second current step size associated with the LSB thereof that is smaller than the first current step size. The combination of the first and second IDACs increases the bit resolution of the first IDAC when driving the first output node with the second IDAC.
摘要翻译： 用于组合多个DAC的输出以提高比特分辨率的方法和装置。 一种用于向可操作以将数字信息转换为模拟值的数据转换器提供增加的位分辨率的方法。 控制第一当前数模（IAC）转换器以向第一输出节点提供电流，第一IDAC具有与其最低有效位（LSB）相关联的第一当前步长。 控制第二IDAC以向第一输出节点提供电流，第二IDAC具有与其LSB的相关联的小于第一当前步长的第二当前步长。 当用第二IDAC驱动第一输出节点时，第一和第二IDAC的组合增加了第一IDAC的位分辨率。
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公开(公告)号：US20050204224A1
公开(公告)日：2005-09-15
申请号：US11114840
申请日：2005-04-26
申请人： Douglas Piasecki , Alvin Storvik
发明人： Douglas Piasecki , Alvin Storvik
IPC分类号： G01R31/28 , G06F7/38 , G06F13/40 , H03K19/173
CPC分类号： G06F13/4072
摘要： A pin interface for an integrated circuit. The pin interface includes logic gates for processing digital signals, and analog lines for carrying analog signals. The pin interface includes circuits for disabling the digital circuits when configured to carry analog signals. A comparator is associated with at least one of the pins for comparing the analog voltage level thereon with a reference voltage.
摘要翻译： 集成电路的引脚接口。 引脚接口包括用于处理数字信号的逻辑门和用于承载模拟信号的模拟线。 引脚接口包括用于在配置为承载模拟信号时禁用数字电路的电路。 比较器与至少一个引脚相关联，用于将其上的模拟电压电平与参考电压进行比较。
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9.发明授权System and method for connecting a master device with multiple groupings of slave devices via a LINBUS network 有权通过LINBUS网络将主设备与多个从设备分组连接的系统和方法公开(公告)号：US07913012B2
公开(公告)日：2011-03-22
申请号：US11967713
申请日：2007-12-31
申请人： Douglas Piasecki , William Hong
发明人： Douglas Piasecki , William Hong
IPC分类号： G06F13/00
CPC分类号： G06F13/4208
摘要： A LINBUS communication network comprises a microcontroller unit containing processing circuitry for performing predefined digital processing functions. LINBUS communication network hardware is located within the microcontroller unit for digitally communicating with an off-chip LINBUS device for transmitting data thereto and receiving data therefrom. A plurality of LINBUS communication network interfaces selectively connects one of a plurality of groups of slave devices to the LINBUS network communications hardware.
摘要翻译： LINBUS通信网络包括包含用于执行预定义数字处理功能的处理电路的微控制器单元。 LINBUS通信网络硬件位于微控制器单元内，用于与片外LINBUS设备进行数字通信，用于向其发送数据并从中接收数据。 多个LINBUS通信网络接口选择性地将多个从设备组中的一个连接到LINBUS网络通信硬件。
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公开(公告)号：US20090322410A1
公开(公告)日：2009-12-31
申请号：US12146352
申请日：2008-06-25
申请人： Thomas S. David , Brian Caloway , Golam Chowdhury , Brent Wilson , Farris Bar , Douglas Piasecki
发明人： Thomas S. David , Brian Caloway , Golam Chowdhury , Brent Wilson , Farris Bar , Douglas Piasecki
IPC分类号： G06F3/044
CPC分类号： G06F3/044 , G06F3/0412 , G06F3/0416
摘要： A capacitive touch sensor circuitry comprises an interface for interconnecting with a plurality of I/O pins that connect to rows and columns of a capacitive sensor array. Monitoring circuitry, responsive to inputs from the plurality of I/O pins, determines when a capacitive switch in the capacitive sensor array has been actuated and stores an indication of the actuation of the capacitive switch. The monitoring circuitry then generates an interrupt responsive to the determined actuation. A control engine controls a manner in which the monitoring circuitry monitors the plurality of I/O pins. The control engine and the monitoring circuitry may be configured to monitor the plurality of I/O pins in a plurality of operating modes.
摘要翻译： 电容式触摸传感器电路包括用于与连接到电容式传感器阵列的行和列的多个I / O引脚互连的接口。 响应于来自多个I / O引脚的输入的监控电路确定电容式传感器阵列中的电容开关何时已被致动并且存储电容开关的致动指示。 监控电路然后响应所确定的致动产生中断。 控制引擎控制监视电路监视多个I / O引脚的方式。 控制引擎和监控电路可以被配置为以多种操作模式监视多个I / O引脚。
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