公开(公告)号：US20080025450A1

公开(公告)日：2008-01-31

申请号：US11772186

申请日：2007-06-30

申请人： DONALD ALFANO ,  BRETT ETTER ,  TIMOTHY DUPUIS

发明人： DONALD ALFANO ,  BRETT ETTER ,  TIMOTHY DUPUIS

IPC分类号： H04L7/04

CPC分类号： H01L23/66 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/1204 ,  H01L2924/12041 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H04B3/542 ,  H04B3/56 ,  H04B2203/542 ,  H04L25/0266 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00

摘要： An integrated circuit isolator for providing data transfer of digital data signals across a voltage isolation barrier includes an integrated circuit package having a first plurality of input data pins on one side of the isolation barrier and a corresponding plurality of output data pins on the other side of the isolation boundary. First circuitry is associated with the first plurality of input data pins and second circuitry is associated with the plurality of output data pins. A communications interface provides across the voltage isolation barrier a first communications channel for communicating data from the first circuitry to the second circuitry and a second communications channel for communicating synchronization clock data from the first circuitry to the second circuitry. The first circuitry is operable to communicate information from input digital data overlapping each other in time and received on two or more of the associated first plurality of input data pins across the first communications channel and to communicate the synchronization clock signal across the second communications channel. The second circuitry is operable to receive the communicated data from the first circuitry and reconstruct the data for output on the ones of the plurality of output data pins corresponding to the two or more of the associated plurality of input data pins from which the data was communicated responsive to the synchronization clock signal.

摘要翻译： 一种用于在电压隔离屏障上提供数字数据信号的数据传输的集成电路隔离器包括：集成电路封装，其具有在隔离屏障的一侧上的第一多个输入数据引脚和在另一侧的相应的多个输出数据引脚 隔离边界。 第一电路与第一组多个输入数据引脚相关联，第二电路与多个输出数据引脚相关联。 通信接口在电压隔离屏障上提供用于将数据从第一电路传送到第二电路的第一通信信道和用于将同步时钟数据从第一电路传送到第二电路的第二通信信道。 第一电路可操作以从时间上彼此重叠的输入数字数据传送信息，并在第一通信信道上的相关联的第一多个输入数据引脚中的两个或更多个上接收信号，并且跨越第二通信信道传送同步时钟信号。 第二电路可操作以从第一电路接收所传送的数据，并且重构数据以输出与多个输入数据引脚相对应的多个输出数据引脚中的两个或多个相关联的多个输入数据引脚，数据从其传送 响应于同步时钟信号。

公开(公告)号：US20070300047A1

公开(公告)日：2007-12-27

申请号：US11772184

申请日：2007-06-30

申请人： DONALD ALFANO ,  DANNY ALLRED ,  DOUGLAS PIASECKI ,  KENNETH FERNALD ,  KA LEUNG ,  BRIAN CALOWAY ,  ALVIN STORVIK ,  PAUL HIGHLEY ,  DOUGLAS HOLBERG

发明人： DONALD ALFANO ,  DANNY ALLRED ,  DOUGLAS PIASECKI ,  KENNETH FERNALD ,  KA LEUNG ,  BRIAN CALOWAY ,  ALVIN STORVIK ,  PAUL HIGHLEY ,  DOUGLAS HOLBERG

IPC分类号： G06F13/00

CPC分类号： G06F13/385 ,  G06F1/08 ,  G06F15/7814 ,  H03M1/122 ,  H03M1/183 ,  H03M1/462 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： A reconfigurable processor includes a processor core for operating on a set of instructions to carry out predefined processes and includes a plurality of input/output pins in addition to a plurality of functional input/output blocks. These functional blocks allow the processing core to interface with the plurality of input/output pins, each of the functional input/output blocks having an associated and predetermined functionality. This functionality comprises the output as a function of the input, the function defined by the functionality. Each of the functional input/output blocks has a requirement for a defined number of the plurality of input/output pins wherein the total of the defined number for all of the plurality of functional input/output blocks exceeds the number of the plurality of input/output pins and wherein the processor core is interfaced with one of the input or output of each of the functional blocks. A reconfigurable interface selectively interfaces between the other of the input or output of the functional blocks and a select one or ones of the plurality of input/output pins, such that the processor core can be interfaced with the select one or ones of the input/output pins. The reconfigurable interface is operable to define how each of the plurality of input/output pins interfaces with the select ones of the plurality of functional blocks and the associated functionality in accordance with configuration information. A non-volatile memory is provided for storing information for use in association with the configuration information, such that the stored information can be altered.

摘要翻译： 可重构处理器包括用于在一组指令上操作以执行预定义的处理的处理器核心，并且除了多个功能输入/输出块之外还包括多个输入/输出引脚。 这些功能块允许处理核与多个输入/输出引脚相连接，每个功能输入/输出块具有相关联的和预定的功能。 该功能包括作为输入的功能的输出，功能定义的功能。 每个功能输入/输出块对多个输入/输出引脚的定义数量要求，其中所有多个功能输入/输出块中的所有定义数目的总数超过多个输入/ 输出引脚，并且其中处理器核心与每个功能块的输入或输出中的一个接口。 可重配置接口选择性地在功能块的输入或输出中的另一个与多个输入/输出引脚中的选择一个或多个输入/输出引脚之间进行接口，使得处理器核可以与选择的一个或多个输入/ 输出引脚。 可重配置接口可操作以根据配置信息定义多个输入/输出引脚中的每一个如何与多个功能块中的选择功能块和相关联的功能接口。 提供非易失性存储器用于存储与配置信息相关联使用的信息，使得可以改变所存储的信息。

公开(公告)号：US20070296478A1

公开(公告)日：2007-12-27

申请号：US11694629

申请日：2007-03-30

申请人： DONALD ALFANO ,  DANNY ALLRED ,  DOUGLAS PIASECKI ,  KENNETH FERNALD ,  KA LEUNG ,  BRIAN CALOWAY ,  ALVIN STORVIK ,  PAUL HIGHLEY ,  DOUGLAS HOLBERG

发明人： DONALD ALFANO ,  DANNY ALLRED ,  DOUGLAS PIASECKI ,  KENNETH FERNALD ,  KA LEUNG ,  BRIAN CALOWAY ,  ALVIN STORVIK ,  PAUL HIGHLEY ,  DOUGLAS HOLBERG

IPC分类号： H03H11/26

CPC分类号： G06F13/385 ,  G06F1/08 ,  G06F15/7814 ,  H03M1/122 ,  H03M1/183 ,  H03M1/462 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： An integrated circuit package includes a processing core for operating on a set of instructions to carry out predefined processes. A plurality of comparators perform compare operations within the integrated circuit package. At least one control register is associated with each of the plurality of comparators. The plurality of comparators are programmable to operate in a plurality of operating modes responsive to control bits established in the at least one control register by the processing core.

摘要翻译： 集成电路封装包括用于对一组指令进行操作以执行预定义的处理的处理核心。 多个比较器执行集成电路封装内的比较操作。 至少一个控制寄存器与多个比较器中的每一个相关联。 多个比较器可编程为响应于由处理核心在至少一个控制寄存器中建立的控制位而以多种操作模式操作。

公开(公告)号：US20060212679A1

公开(公告)日：2006-09-21

申请号：US11381707

申请日：2006-05-04

申请人： Donald Alfano ,  Danny Allred ,  Douglas Piasecki ,  Kenneth Fernald ,  Ka Leung ,  Brian Caloway ,  Alvin Storvik ,  Paul Highley ,  Douglas Holberg

发明人： Donald Alfano ,  Danny Allred ,  Douglas Piasecki ,  Kenneth Fernald ,  Ka Leung ,  Brian Caloway ,  Alvin Storvik ,  Paul Highley ,  Douglas Holberg

IPC分类号： G06F15/00

CPC分类号： G06F13/385 ,  G06F1/08 ,  G06F15/7814 ,  H03M1/122 ,  H03M1/183 ,  H03M1/462 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： Field programmable mixed-signal integrated circuit. A reconfigurable processor system includes a processor core is provided that operates on a set of instructions to carry out predefined processes. A plurality of input/output pins are provided for interfacing with external signals. A reconfigurable interface interfaces between the processor core and the input/output pins. The reconfigurable interface is operable to define how each of the plurality of input/output pins interfaces with the processor core and the functionality associated therewith.

摘要翻译： 现场可编程混合信号集成电路。 可重新配置的处理器系统包括提供处理器核心，其操作一组指令以执行预定义的过程。 提供多个输入/输出引脚用于与外部信号进行接口。 处理器核心和输入/输出引脚之间的可重配置接口接口。 可重构接口可操作以定义多个输入/输出引脚中的每一个如何与处理器核心和与其相关联的功能。

公开(公告)号：US20060104096A1

公开(公告)日：2006-05-18

申请号：US10987569

申请日：2004-11-12

申请人： Donald Alfano

发明人： Donald Alfano

IPC分类号： H02M1/12

CPC分类号： H02M7/003

摘要： A power supply for a portable electronic device includes power circuitry for converting AC power from an AC power supply to DC power for the portable device. A processor is coupled to the power circuitry for receiving a plurality of parameters. The processor determines the status of the power supply responsive to the plurality of the parameters and generates a signal to drive an indicator providing an indication of the status of the power supply.

摘要翻译： 用于便携式电子设备的电源包括用于将来自AC电源的AC电力转换成用于便携式设备的DC电力的电力电路。 处理器耦合到电源电路，用于接收多个参数。 所述处理器响应于所述多个参数来确定所述电源的状态，并且产生用于驱动指示器的信号以提供所述电源的状态的指示。

公开(公告)号：US20060005054A1

公开(公告)日：2006-01-05

申请号：US10881793

申请日：2004-06-30

申请人： Kenneth Fernald ,  Donald Alfano

发明人： Kenneth Fernald ,  Donald Alfano

IPC分类号： G06F1/26

CPC分类号： G06F1/3203

摘要： A microcontroller unit (MCU) is disclosed with a stand-alone Real Time Clock (RTC). The MCU includes a processing circuit for receiving digital information and processing said received digital information. A primary clock circuit provides the timing for the processing circuit. A power control circuit controls the power to the processing circuit and the primary clock circuit to control the operation thereof to operate in at least a full power mode drawing a full power level from a supply voltage input and a reduced power mode drawing less than the full power level from the supply voltage input. A stand-alone RTC circuit is also provided, the stand-alone RTC circuit including an RTC clock circuit operating independent of the primary clock circuit. A timer clocked by the RTC clock circuit is operable to increment a stored time value for output therefrom, the RTC clock circuit having a defined time base. An input/output (I/O) device provides access by the processing circuit to the results output by the timer. A power management circuitry manages the power to the stand-alone RTC circuit, such that the RTC clock circuit, the timer, and the I/O device operate regardless of the power mode of operation of the processing circuitry and the primary clock circuit.

摘要翻译： 公开了具有独立实时时钟（RTC）的微控制器单元（MCU）。 MCU包括用于接收数字信息并处理所接收的数字信息的处理电路。 主时钟电路为处理电路提供定时。 电源控制电路控制处理电路和主时钟电路的电源，以控制其工作在至少全功率模式下工作，从供电电压输入和低功耗模式绘制小于全功率模式 功率电平从电源电压输入。 还提供独立的RTC电路，独立的RTC电路包括独立于主时钟电路工作的RTC时钟电路。 由RTC时钟电路计时钟的定时器可操作以增加存储的时间值以便从其输出，RTC时钟电路具有确定的时基。 输入/输出（I / O）设备提供处理电路对定时器输出的结果的访问。 电源管理电路管理独立RTC电路的电源，使得RTC时钟电路，定时器和I / O设备无论处理电路和主时钟电路的功率工作模式如何都工作。

公开(公告)号：US20070103357A1

公开(公告)日：2007-05-10

申请号：US11618644

申请日：2006-12-29

申请人： DONALD ALFANO ,  DANNY ALLRED ,  DOUGLAS PIASECKI ,  KENNETH FERNALD ,  KA LEUNG ,  BRIAN CALOWAY ,  ALVIN STORVIK ,  PAUL HIGHLEY ,  DOUGLAS HOLBERG

发明人： DONALD ALFANO ,  DANNY ALLRED ,  DOUGLAS PIASECKI ,  KENNETH FERNALD ,  KA LEUNG ,  BRIAN CALOWAY ,  ALVIN STORVIK ,  PAUL HIGHLEY ,  DOUGLAS HOLBERG

IPC分类号： H03M1/12

CPC分类号： G06F13/385 ,  G06F1/08 ,  G06F15/7814 ,  H03M1/122 ,  H03M1/183 ,  H03M1/462 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： A method for converting analog data to digital data is disclosed. The method includes operating an analog-to-digital data converter in a tracking mode to sample an input signal and in a convert mode to convert the sampled input signal after sampling to a digital signal. The analog-to-digital data converter is controlled with a controller to operate in different modes of operation by providing at least one step wherein the tracking mode of operation is controlled to initiate at a predetermined time to begin the sampling operation.

摘要翻译： 公开了一种将模拟数据转换为数字数据的方法。 该方法包括以跟踪模式操作模拟数字数据转换器，以对输入信号进行采样，并以转换模式对采样后的采样输入信号进行数字信号转换。 模拟数字数据转换器由控制器控制，以通过提供至少一个步骤操作在不同的操作模式，其中跟踪操作模式被控制以在预定时间开始以开始采样操作。

公开(公告)号：US20060244570A1

公开(公告)日：2006-11-02

申请号：US11394909

申请日：2006-03-31

申请人： Kafai Leung ,  Ka Leung ,  Donald Alfano

发明人： Kafai Leung ,  Ka Leung ,  Donald Alfano

IPC分类号： G05B11/01

CPC分类号： H02J13/0062 ,  H02J1/08 ,  H02J13/0003 ,  H02M3/33515 ,  H02M3/33576 ,  H02M2001/008 ,  H03K3/356121 ,  H03K3/35613 ,  H03K7/08 ,  H03M1/363 ,  Y10T307/461 ,  Y10T307/469

摘要： A distributed power system for delivering DC power to a plurality of loads. A plurality of power converter modules having associated therewith a DC/DC power conversion operation are provided, each disposed proximate an associated one of the loads, each of said converter modules having associated therewith a switching pulse generator for generating switching pulses. A distributed power line distributes input power to each of the modules. A data communication line distributes command data between the modules. Each of the modules includes a power regulation section for receiving the input power to generate a DC output by controlling the operation of the switching pulse generator. It also includes a processing section for interfacing with the data communication line for interfacing with the commands, the processing function operating in at least a slave mode to receive commands from the data communication bus. At least one of the modules operates in both a slave mode and a master mode. In the master mode, the processing section generates commands for transmission over the data communication line to an addressed one of the other of the modules and internally for use in the local slave mode of operation. The processing section in the slave mode of operation is operable to configure and monitor the operation of the power regulation section.

摘要翻译： 一种用于将DC电力传送到多个负载的分布式电力系统。 提供了具有与其相关联的DC / DC功率转换操作的多个功率转换器模块，每个功率转换器模块设置在相关联的一个负载附近，每个所述转换器模块具有与其相关联的用于产生开关脉冲的开关脉冲发生器。 分布式电力线将输入电力分配给每个模块。 数据通信线路在模块之间分配命令数据。 每个模块包括功率调节部分，用于通过控制开关脉冲发生器的操作来接收输入功率以产生DC输出。 它还包括一个处理部分，用于与数据通信线对接，用于与命令进行接口，处理功能以至少从属模式操作，以从数据通信总线接收命令。 至少一个模块在从模式和主模式下都工作。 在主模式下，处理部分生成用于通过数据通信线路发送到另一个模块中寻址的另一个模块的命令，并在内部生成用于本地从属操作模式的命令。 在从属操作模式下的处理部分可操作以配置和监视功率调节部分的操作。

公开(公告)号：US20060172783A1

公开(公告)日：2006-08-03

申请号：US11394789

申请日：2006-03-31

申请人： Kafai Leung ,  Ka Leung ,  Donald Alfano

发明人： Kafai Leung ,  Ka Leung ,  Donald Alfano

IPC分类号： H04B1/38 ,  H04M1/00

CPC分类号： H02M3/33515 ,  H02M3/33576 ,  H03K3/356121 ,  H03K3/35613 ,  H03K7/08 ,  H03M1/363

摘要： A power converter is disclosed for receiving an input voltage and converting it to a DC output voltage at a different voltage level than the input voltage. It includes a switching power converter for receiving the input voltage on an input and converting the input voltage to an output as the DC output voltage in response to pulse control signals. A switching controller is provided for generating the pulse control signals during a switching cycle and a processor controls the switching controller to define the length and initiation of the switching cycle. A communication interface interfaces with a first data communication bus for receiving data therefrom and with a second communication bus for receiving timing information therefrom. The processor and the switching controller operate in either a first operating mode to control the switching controller and the generation of the pulse control signals independent of timing information, or in a second operating mode to control the timing of the generation of the pulse control signals generated by the switching controller in response to timing information received from the communication bus.

摘要翻译： 公开了一种用于接收输入电压并将其转换成与输入电压不同的电压电平的DC输出电压的功率转换器。 它包括用于接收输入端的输入电压的开关电源转换器，并且响应于脉冲控制信号将输入电压转换为作为直流输出电压的输出。 提供开关控制器用于在开关周期期间产生脉冲控制信号，并且处理器控制开关控制器以限定开关周期的长度和启动。 通信接口与第一数据通信总线接口，用于从其接收数据，并具有用于从其接收定时信息的第二通信总线。 处理器和开关控制器在第一操作模式下操作以控制开关控制器和独立于定时信息的脉冲控制信号的产生，或者在第二操作模式中控制生成的脉冲控制信号的定时 由开关控制器响应于从通信总线接收的定时信息。

公开(公告)号：US20060022731A1

公开(公告)日：2006-02-02

申请号：US11096043

申请日：2005-03-31

申请人： Kafai Leung ,  Ka Leung ,  Donald Alfano

发明人： Kafai Leung ,  Ka Leung ,  Donald Alfano

IPC分类号： H03K3/017

CPC分类号： H03K7/08 ,  H02M1/32 ,  H02M3/157

摘要： An apparatus for providing over current protection for a digital pulse width modulator is disclosed. The apparatus includes first logic circuitry for generating a primary interrupt indicating that a detected output current is greater than a threshold current. Second logic circuitry generates a secondary input responsive to the occurrence to the primary interrupt for a predetermined number of times.

摘要翻译： 公开了一种用于为数字脉宽调制器提供过流保护的装置。 该装置包括用于产生指示检测到的输出电流大于阈值电流的主中断的第一逻辑电路。 第二逻辑电路响应于主中断的发生预定次数产生次级输入。