公开(公告)号：US06922164B1

公开(公告)日：2005-07-26

申请号：US10815416

申请日：2004-03-31

申请人： Douglas Piasecki ,  Douglas Holberg ,  Ka Y. Leung ,  Donald E. Alfano

发明人： Douglas Piasecki ,  Douglas Holberg ,  Ka Y. Leung ,  Donald E. Alfano

IPC分类号： H03M1/34 ,  H03M1/46

CPC分类号： H03M1/462

摘要： SAR analog-to-digital converter with abort function. A method for increasing the throughput of a data converter decision is disclosed. First, a data conversion operation is initiated to convert analog signals on an analog input on a data converter to digital data by sampling the analog signals on the analog signal input and then converting the sampled analog signals to digital data with a predetermined data conversion algorithm in a data conversion operation. The digital output of the data converter is compared to a threshold voltage value. When the output of the data converter is determined by the step of comparing to meet a predetermined relationship relative to the threshold voltage, the data conversion operation is terminated prior to the complete execution of the data conversion operation on the sampled analog signals.

摘要翻译： 具有中止功能的SAR模数转换器。 公开了一种用于增加数据转换器决定的吞吐量的方法。 首先，通过对模拟信号输入上的模拟信号进行采样，然后利用预定的数据转换算法将采样的模拟信号转换成数字数据，开始数据转换操作以将数据转换器上的模拟输入上的模拟信号转换成数字数据 数据转换操作。 将数据转换器的数字输出与阈值电压值进行比较。 当通过比较步骤确定数据转换器的输出以达到相对于阈值电压的预定关系时，在对采样的模拟信号完成数据转换操作之后终止数据转换操作。

公开(公告)号：US07660968B2

公开(公告)日：2010-02-09

申请号：US11772184

申请日：2007-06-30

申请人： Donald E. Alfano ,  Danny J. Allred ,  Douglas S. Piasecki ,  Kenneth W. Fernald ,  Ka Y. Leung ,  Brian Caloway ,  Alan Storvik ,  Paul Highley ,  Douglas R. Holberg

发明人： Donald E. Alfano ,  Danny J. Allred ,  Douglas S. Piasecki ,  Kenneth W. Fernald ,  Ka Y. Leung ,  Brian Caloway ,  Alan Storvik ,  Paul Highley ,  Douglas R. Holberg

IPC分类号： G06F13/00

CPC分类号： G06F13/385 ,  G06F1/08 ,  G06F15/7814 ,  H03M1/122 ,  H03M1/183 ,  H03M1/462 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： A reconfigurable processor includes a processor core for operating on a set of instructions to carry out predefined processes and includes a plurality of input/output pins in addition to a plurality of functional input/output blocks. These functional blocks allow the processing core to interface with the plurality of input/output pins, each of the functional input/output blocks having an associated and predetermined functionality. This functionality comprises the output as a function of the input, the function defined by the functionality. Each of the functional input/output blocks has a requirement for a defined number of the plurality of input/output pins wherein the total of the defined number for all of the plurality of functional input/output blocks exceeds the number of the plurality of input/output pins and wherein the processor core is interfaced with one of the input or output of each of the functional blocks. A reconfigurable interface selectively interfaces between the other of the input or output of the functional blocks and a select one or ones of the plurality of input/output pins, such that the processor core can be interfaced with the select one or ones of the input/output pins. The reconfigurable interface is operable to define how each of the plurality of input/output pins interfaces with the select ones of the plurality of functional blocks and the associated functionality in accordance with configuration information. A non-volatile memory is provided for storing information for use in association with the configuration information, such that the stored information can be altered.

摘要翻译： 可重构处理器包括用于在一组指令上操作以执行预定义的处理的处理器核心，并且除了多个功能输入/输出块之外还包括多个输入/输出引脚。 这些功能块允许处理核与多个输入/输出引脚相连接，每个功能输入/输出块具有相关联的和预定的功能。 该功能包括作为输入的功能的输出，功能定义的功能。 每个功能输入/输出块对多个输入/输出引脚的定义数量要求，其中所有多个功能输入/输出块中的所有定义数目的总数超过多个输入/ 输出引脚，并且其中处理器核心与每个功能块的输入或输出中的一个接口。 可重配置接口选择性地在功能块的输入或输出中的另一个与多个输入/输出引脚中的选择一个或多个输入/输出引脚之间进行接口，使得处理器核可以与选择的一个或多个输入/ 输出引脚。 可重配置接口可操作以根据配置信息定义多个输入/输出引脚中的每一个如何与多个功能块中的选择功能块和相关联的功能接口。 提供非易失性存储器用于存储与配置信息相关联使用的信息，使得可以改变所存储的信息。

公开(公告)号：US07640455B2

公开(公告)日：2009-12-29

申请号：US11172482

申请日：2005-06-30

申请人： Ka Y. Leung ,  Kafai Leung ,  Donald E. Alfano

发明人： Ka Y. Leung ,  Kafai Leung ,  Donald E. Alfano

IPC分类号： G06F11/00

CPC分类号： H02M3/33515 ,  H02M3/157 ,  H02M2001/0012 ,  H02M2001/007

摘要： An apparatus for forcing outputs of a digital controller of a switching power converter to a safe state during shutdown of the switching power converter is described. The apparatus includes a multiplexer providing an output signal of the digital controller and having a first input of the multiplexer connected to receive a switching control signal control signal from the digital controller. The multiplexer also has a plurality of inputs from control registers providing programmed safe state values. The multiplexer connects one of the first input or the inputs from the plurality of control registers to the output of the multiplexer responsive to a multiplexer control signal. Control logic generates the multiplexer control signal responsive to at least one of an end of frame interrupt, an over current interrupt, an enable interrupt or a software bypass signal.

摘要翻译： 描述了用于在切换功率转换器关闭期间将开关电源转换器的数字控制器的输出强制到安全状态的装置。 该装置包括多路复用器，提供数字控制器的输出信号，并具有多路复用器的第一输入端，用于从数字控制器接收切换控制信号控制信号。 复用器还具有提供编程的安全状态值的来自控制寄存器的多个输入。 多路复用器响应于多路复用器控制信号将来自多个控制寄存器的第一输入或输入中的一个连接到多路复用器的输出。 响应于帧中断，过电流中断，使能中断或软件旁路信号中的至少一个，控制逻辑产生多路复用器控制信号。

公开(公告)号：US07446430B2

公开(公告)日：2008-11-04

申请号：US11394909

申请日：2006-03-31

申请人： Kafai Leung ,  Ka Y. Leung ,  Donald E. Alfano

发明人： Kafai Leung ,  Ka Y. Leung ,  Donald E. Alfano

IPC分类号： H02J1/00

CPC分类号： H02J13/0062 ,  H02J1/08 ,  H02J13/0003 ,  H02M3/33515 ,  H02M3/33576 ,  H02M2001/008 ,  H03K3/356121 ,  H03K3/35613 ,  H03K7/08 ,  H03M1/363 ,  Y10T307/461 ,  Y10T307/469

摘要： A distributed power system for delivering DC power to a plurality of loads. A plurality of power converter modules having associated therewith a DC/DC power conversion operation are provided, each disposed proximate an associated one of the loads, each of said converter modules having associated therewith a switching pulse generator for generating switching pulses. A distributed power line distributes input power to each of the modules. A data communication line distributes command data between the modules. Each of the modules includes a power regulation section for receiving the input power to generate a DC output by controlling the operation of the switching pulse generator. It also includes a processing section for interfacing with the data communication line for interfacing with the commands, the processing function operating in at least a slave mode to receive commands from the data communication bus. At least one of the modules operates in both a slave mode and a master mode. In the master mode, the processing section generates commands for transmission over the data communication line to an addressed one of the other of the modules and internally for use in the local slave mode of operation. The processing section in the slave mode of operation is operable to configure and monitor the operation of the power regulation section.

摘要翻译： 一种用于将DC电力传送到多个负载的分布式电力系统。 提供了具有与其相关联的DC / DC功率转换操作的多个功率转换器模块，每个功率转换器模块设置在相关联的一个负载附近，每个所述转换器模块具有与其相关联的用于产生开关脉冲的开关脉冲发生器。 分布式电力线将输入电力分配给每个模块。 数据通信线路在模块之间分配命令数据。 每个模块包括功率调节部分，用于通过控制开关脉冲发生器的操作来接收输入功率以产生DC输出。 它还包括一个处理部分，用于与数据通信线对接，用于与命令进行接口，处理功能以至少从属模式操作，以从数据通信总线接收命令。 至少一个模块在从模式和主模式下都工作。 在主模式下，处理部分生成用于通过数据通信线路发送到另一个模块中寻址的另一个模块的命令，并在内部生成用于本地从属操作模式的命令。 在从属操作模式下的处理部分可操作以配置和监视功率调节部分的操作。

公开(公告)号：US07171542B1

公开(公告)日：2007-01-30

申请号：US09885459

申请日：2001-06-19

申请人： Donald E. Alfano ,  Danny Allred ,  Douglas S. Piasecki ,  Kenneth W. Fernald ,  Ka Y Leung ,  Brian Caloway ,  Alvin Storvik ,  Paul Highley ,  Douglas R Holberg

发明人： Donald E. Alfano ,  Danny Allred ,  Douglas S. Piasecki ,  Kenneth W. Fernald ,  Ka Y Leung ,  Brian Caloway ,  Alvin Storvik ,  Paul Highley ,  Douglas R Holberg

IPC分类号： G06F13/00

CPC分类号： G06F13/385 ,  G06F1/08 ,  G06F15/7814 ,  H03M1/122 ,  H03M1/183 ,  H03M1/462 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： A reconfigurable processor system n an intergrated circuit includes a processor core that operates on a set of instructions to carry out predefined processes. A plurality of input/output pins are provided for interfacing with external signals. A reconfigurable interface interfaces between the processor core and the input/output pins through select ones of a plurality of functional blocks. The reconfigurable interface is operable to define how each of the plurality of input/output pins interfaces with the processor core an the functionality associated therewith. The functional blocks provide the interface of the processor core with the input/output pins.

摘要翻译： 集成电路中的可重构处理器系统包括对一组指令进行操作以执行预定义的处理的处理器核心。 提供多个输入/输出引脚用于与外部信号进行接口。 可重新配置的接口通过多个功能块中的选择的接口在处理器核心和输入/输出引脚之间进行接口。 可重构接口可操作以定义多个输入/输出引脚中的每一个如何与处理器核心与处理器核心相连接的功能。 功能块提供处理器内核与输入/输出引脚的接口。

公开(公告)号：US07502240B2

公开(公告)日：2009-03-10

申请号：US11396145

申请日：2006-03-31

申请人： Kafai Leung ,  Ka Y. Leung ,  Donald E. Alfano

发明人： Kafai Leung ,  Ka Y. Leung ,  Donald E. Alfano

IPC分类号： H02J1/10 ,  H02J1/00

CPC分类号： H02M3/33515 ,  H02M3/33576 ,  H03K3/356121 ,  H03K3/35613 ,  H03K7/08 ,  H03M1/363 ,  Y10T307/477

摘要： A distributed power system for delivering DC power to a plurality of loads. A plurality of switching DC/DC converter modules are provided, each disposed proximate one of the loads, and each having associated therewith a switching pulse generator for generating switching pulses. A distributed power line distributes input power to each of the modules and a data communication line distributes command data between the modules, each of the modules uniquely addressable over the data communication line. A timing communication line is also provided for distributing timing information to each of the switching pulse generators. A master controller generates commands and communicates them to the data modules over the data communication line, the master controller operable to generate timing information over the timing communication line to each of the modules for controlling the associated switching pulse generator.

摘要翻译： 一种用于将DC电力传送到多个负载的分布式电力系统。 提供了多个开关DC / DC转换器模块，每个开关DC / DC转换器模块设置在靠近其中一个负载的位置，并且每个具有相关联的开关脉冲发生器用于产生开关脉冲。 分布式电力线将输入电力分配给每个模块，并且数据通信线路在模块之间分配命令数据，每个模块可以通过数据通信线路唯一地寻址。 还提供定时通信线路，用于将定时信息分配给每个开关脉冲发生器。 主控制器产生命令并通过数据通信线路将其传送到数据模块，主控制器可操作以通过定时通信线路产生定时信息到每个模块以控制相关联的开关脉冲发生器。

公开(公告)号：US20080317106A1

公开(公告)日：2008-12-25

申请号：US12165011

申请日：2008-06-30

申请人： Ka Y. Leung ,  Donald E. Alfano ,  David Bresemann

发明人： Ka Y. Leung ,  Donald E. Alfano ,  David Bresemann

IPC分类号： H04B1/40

CPC分类号： G06F13/4072 ,  G06F13/4278 ,  H01L2224/05554 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

摘要： An integrated circuit comprises a first microcontroller unit for executing instructions in accordance with a first clock frequency. The microcontroller located on a first die and includes a first processing core for providing a parallel stream of data in accordance with the first clock frequency. A second microcontroller unit executes instructions in accordance with the first clock frequency. The second microcontroller is located on a second die and includes a second processing core for receiving the parallel stream of data in accordance with the first clock frequency. Capacitive isolation circuitry connected with the first microcontroller unit and the second microcontroller unit provides a high voltage isolation link between the first and the second microcontroller units. The capacitive isolation circuitry distributing a first portion of a high voltage isolation signal across a first group of capacitors associated with the first microcontroller unit and distributes a second portion of the high voltage isolation signal across a second group of capacitors associated with the second microcontroller unit. The capacitive isolation circuitry further transmits data from the parallel data stream between the first microcontroller and the second microcontroller in a serial data stream in accordance with the second clock frequency.

摘要翻译： 集成电路包括用于根据第一时钟频率执行指令的第一微控制器单元。 微控制器位于第一管芯上并且包括用于根据第一时钟频率提供并行数据流的第一处理核心。 第二微控制器单元根据第一时钟频率执行指令。 第二微控制器位于第二管芯上，并且包括用于根据第一时钟频率接收并行数据流的第二处理核。 与第一微控制器单元和第二微控制器单元连接的电容隔离电路在第一和第二微控制器单元之间提供高电压隔离链路。 电容隔离电路将高电压隔离信号的第一部分跨越与第一微控制器单元相关联的第一组电容器分配，并将第二部分高电压隔离信号分配到与第二微控制器单元相关联的第二组电容器上。 电容隔离电路还根据第二时钟频率在串行数据流中从第一微控制器和第二微控制器之间的并行数据流传输数据。

公开(公告)号：US08441325B2

公开(公告)日：2013-05-14

申请号：US12494618

申请日：2009-06-30

申请人： Phil A. Callahan ,  Ahsan Javed ,  Zhiwei Dong ,  Axel Thomsen ,  Donald E. Alfano ,  Timothy Dupuis ,  Ka Y. Leung

发明人： Phil A. Callahan ,  Ahsan Javed ,  Zhiwei Dong ,  Axel Thomsen ,  Donald E. Alfano ,  Timothy Dupuis ,  Ka Y. Leung

IPC分类号： H03H2/00 ,  H04B3/00

CPC分类号： H01L24/48 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49575 ,  H01L23/642 ,  H01L23/66 ,  H01L24/06 ,  H01L24/49 ,  H01L25/0655 ,  H01L2223/6611 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H04B2203/5491 ,  H01L2224/45099 ,  H01L2924/00

摘要： An isolator that includes first and second substantially identical circuitry galvanically isolated from each other and each having at least one communications channel thereon for communicating signals across an isolation boundary therebetween and each of said first and second circuitry having configurable functionality associated with the operation thereof. A coupling device is provided for coupling signal across the isolation boundary between the at least one communication channels of the first and second circuitry. First and second configuration memories are provided, each associated with a respective one of the first and second circuitry. First and second configuration control devices are provided, each associated with a respective one of the first and second circuitry and each configuring the functionality of the associated one of the first and second circuitry. The first and second configurable memories have stored therein complementary configuration information to control each of the functionalities of the first and second circuitry to operate in a complementary manner for communication of signals across the isolation boundary.

摘要翻译： 一种隔离器，其包括彼此电隔离的第一和第二基本相同的电路，并且每个具有至少一个用于在其间的隔离边界传送信号的通信信道，所述第一和第二电路中的每一个具有与其操作相关联的可配置功能。 提供耦合装置用于在第一和第二电路的至少一个通信信道之间的隔离边界上耦合信号。 提供第一和第二配置存储器，每个与第一和第二电路中的相应一个相关联。 提供第一和第二配置控制设备，每个配置控制设备与第一和第二电路中的相应一个相关联，并且每个配置控制设备配置第一和第二电路中相关联的一个的功能。 第一和第二可配置存储器在其中存储有互补配置信息，以控制第一和第二电路的每个功能以互补的方式进行操作，用于跨越隔离边界的信号通信。

公开(公告)号：US07498962B2

公开(公告)日：2009-03-03

申请号：US11618644

申请日：2006-12-29

申请人： Donald E. Alfano ,  Danny J. Allred ,  Douglas S. Piasecki ,  Kenneth W. Fernald ,  Ka Y. Leung ,  Brian Caloway ,  Alvin Storvik ,  Paul Highley ,  Douglas R. Holberg

发明人： Donald E. Alfano ,  Danny J. Allred ,  Douglas S. Piasecki ,  Kenneth W. Fernald ,  Ka Y. Leung ,  Brian Caloway ,  Alvin Storvik ,  Paul Highley ,  Douglas R. Holberg

IPC分类号： H03M1/00

CPC分类号： G06F13/385 ,  G06F1/08 ,  G06F15/7814 ,  H03M1/122 ,  H03M1/183 ,  H03M1/462 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： A method for converting analog data to digital data includes operating an analog-to-digital data converter in a tracking mode to sample an input signal and in a convert mode to convert the sampled input signal after sampling to a digital signal. The analog-to-digital data converter is controlled with a controller to operate in different modes of operation by providing at least one step wherein the tracking mode of operation is controlled to initiate at a predetermined time to begin the sampling operation.

摘要翻译： 一种将模拟数据转换为数字数据的方法包括以跟踪模式操作模拟数字数据转换器，以对输入信号进行采样，并以转换模式将采样后的采样输入信号转换为数字信号。 模拟数字数据转换器由控制器控制，以通过提供至少一个步骤操作在不同的操作模式，其中跟踪操作模式被控制以在预定时间开始以开始采样操作。

公开(公告)号：US07821428B2

公开(公告)日：2010-10-26

申请号：US12165011

申请日：2008-06-30

申请人： Ka Y. Leung ,  Donald E. Alfano ,  David P. Bresemann

发明人： Ka Y. Leung ,  Donald E. Alfano ,  David P. Bresemann

IPC分类号： H03M9/00

CPC分类号： G06F13/4072 ,  G06F13/4278 ,  H01L2224/05554 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

摘要： An integrated circuit comprises a first microcontroller unit for executing instructions in accordance with a first clock frequency. The microcontroller located on a first die and includes a first processing core for providing a parallel stream of data in accordance with the first clock frequency. A second microcontroller unit executes instructions in accordance with the first clock frequency. The second microcontroller is located on a second die and includes a second processing core for receiving the parallel stream of data in accordance with the first clock frequency. Capacitive isolation circuitry connected with the first microcontroller unit and the second microcontroller unit provides a high voltage isolation link between the first and the second microcontroller units. The capacitive isolation circuitry distributing a first portion of a high voltage isolation signal across a first group of capacitors associated with the first microcontroller unit and distributes a second portion of the high voltage isolation signal across a second group of capacitors associated with the second microcontroller unit. The capacitive isolation circuitry further transmits data from the parallel data stream between the first microcontroller and the second microcontroller in a serial data stream in accordance with the second clock frequency.

摘要翻译： 集成电路包括用于根据第一时钟频率执行指令的第一微控制器单元。 微控制器位于第一管芯上并且包括用于根据第一时钟频率提供并行数据流的第一处理核心。 第二微控制器单元根据第一时钟频率执行指令。 第二微控制器位于第二管芯上，并且包括用于根据第一时钟频率接收并行数据流的第二处理核。 与第一微控制器单元和第二微控制器单元连接的电容隔离电路在第一和第二微控制器单元之间提供高电压隔离链路。 电容隔离电路将高电压隔离信号的第一部分跨越与第一微控制器单元相关联的第一组电容器分配，并将第二部分高电压隔离信号分配到与第二微控制器单元相关联的第二组电容器上。 电容隔离电路还根据第二时钟频率在串行数据流中从第一微控制器和第二微控制器之间的并行数据流传输数据。