公开(公告)号：US09865381B2

公开(公告)日：2018-01-09

申请号：US15113397

申请日：2015-01-02

Applicant: EPCOS AG

Inventor： Yasuharu Miyauchi ,  Pavol Dudesek ,  Christian Faistauer ,  Gerhard Fuchs ,  Stefan Obermair ,  Klaus-Dieter Aichholzer ,  Christian Block ,  Sebastian Brunner

IPC: H01C7/10 ,  H01C7/12 ,  C03C3/089 ,  H01C7/112 ,  H01C7/18 ,  H01C17/28 ,  H01L25/16

CPC classification number: H01C7/12 ,  C03C3/089 ,  H01C7/1006 ,  H01C7/112 ,  H01C7/18 ,  H01C17/285 ,  H01L25/167 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A chip and a method for manufacturing a chip are disclosed. In an embodiment, the chip includes a varistor layer composed of zinc oxide, a multilayered electrode structure which realizes a varistor function in the varistor layer and at least two solderable or bondable external contacts on a first main surface of the varistor layer. The chip further includes a glass layer disposed on the first main surface leaving only the external contacts uncovered, wherein the glass layer includes, as main constituents, oxides of Si and/or Ge, B and K, which in total have at least 70% by weight of the constituents of the glass layer, and wherein the glass layer is substantially free of Al, Ga, Cr and Ti.

公开(公告)号：US20170011827A1

公开(公告)日：2017-01-12

申请号：US15113397

申请日：2015-01-02

Applicant: EPCOS AG

Inventor： Yasuharu Miyauchi ,  Pavol Dudesek ,  Christian Faistauer ,  Gerhard Fuchs ,  Stefan Obermair ,  Klaus-Dieter Aichholzer ,  Christian Block ,  Sebastian Brunner

IPC: H01C7/12 ,  C03C3/089 ,  H01C7/10 ,  H01C7/18 ,  H01C17/28

CPC classification number: H01C7/12 ,  C03C3/089 ,  H01C7/1006 ,  H01C7/112 ,  H01C7/18 ,  H01C17/285 ,  H01L25/167 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A chip and a method for manufacturing a chip are disclosed. In an embodiment, the chip includes a varistor layer composed of zinc oxide, a multilayered electrode structure which realizes a varistor function in the varistor layer and at least two solderable or bondable external contacts on a first main surface of the varistor layer. The chip further includes a glass layer disposed on the first main surface leaving only the external contacts uncovered, wherein the glass layer includes, as main constituents, oxides of Si and/or Ge, B and K, which in total have at least 70% by weight of the constituents of the glass layer, and wherein the glass layer is substantially free of Al, Ga, Cr and Ti.

Abstract translation: 公开了一种芯片和芯片的制造方法。 在一个实施例中，芯片包括由氧化锌组成的可变电阻层，在压敏电阻层中实现变阻器功能的多层电极结构以及可变阻抗层的第一主表面上的至少两个可焊接或可接合的外部触点。 芯片还包括设置在第一主表面上的玻璃层，仅留下未覆盖的外部触点，其中玻璃层主要包括Si和/或Ge，B和K的氧化物，其总共具有至少70％ 的玻璃层的成分，并且其中玻璃层基本上不含Al，Ga，Cr和Ti。