公开(公告)号：US20190013149A1

公开(公告)日：2019-01-10

申请号：US16079403

申请日：2017-01-16

Applicant: EPCOS AG

Inventor： Pavol Dudesek

IPC: H01G4/12 ,  H01G4/33 ,  H01G4/30 ,  H01G4/10 ,  C04B35/457 ,  C04B35/462 ,  C04B35/48

Abstract: A dielectric ceramic composition, a method for producing a dieelctric composition and the use of the dielectric composition are disclosed. In an embodiment a ceramic composition includes a main component with a quantity ratio Mg(1+x)(1−y)O3+xA(1+x)ySi(1−z)Dz and a remainder comprising contaminants, wherein 0.01×0.30, wherein 0.00≤y≤0.20, and wherein 0.00≤z≤1.00.

公开(公告)号：US10389105B2

公开(公告)日：2019-08-20

申请号：US15110701

申请日：2015-01-15

Applicant: EPCOS AG

Inventor： Manfred Schweinzger ,  Stefan Obermair ,  Pavol Dudesek

IPC: H01T4/12 ,  H02H3/20

Abstract: An overvoltage protection element and a method for producing an overvoltage protection element is disclosed. In an embodiment, the overvoltage protection element includes a first electrode, a second electrode and a discharge region arranged between the first electrode and the second electrode, wherein a porous discharge dielectric is arranged in the discharge region, and wherein the overvoltage protection element is configured to discharge a gas in pores of the discharge dielectric and produce an electrically conductive connection between the first electrode and the second electrode.

公开(公告)号：US09865381B2

公开(公告)日：2018-01-09

申请号：US15113397

申请日：2015-01-02

Applicant: EPCOS AG

Inventor： Yasuharu Miyauchi ,  Pavol Dudesek ,  Christian Faistauer ,  Gerhard Fuchs ,  Stefan Obermair ,  Klaus-Dieter Aichholzer ,  Christian Block ,  Sebastian Brunner

IPC: H01C7/10 ,  H01C7/12 ,  C03C3/089 ,  H01C7/112 ,  H01C7/18 ,  H01C17/28 ,  H01L25/16

CPC classification number: H01C7/12 ,  C03C3/089 ,  H01C7/1006 ,  H01C7/112 ,  H01C7/18 ,  H01C17/285 ,  H01L25/167 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A chip and a method for manufacturing a chip are disclosed. In an embodiment, the chip includes a varistor layer composed of zinc oxide, a multilayered electrode structure which realizes a varistor function in the varistor layer and at least two solderable or bondable external contacts on a first main surface of the varistor layer. The chip further includes a glass layer disposed on the first main surface leaving only the external contacts uncovered, wherein the glass layer includes, as main constituents, oxides of Si and/or Ge, B and K, which in total have at least 70% by weight of the constituents of the glass layer, and wherein the glass layer is substantially free of Al, Ga, Cr and Ti.

公开(公告)号：US20160329698A1

公开(公告)日：2016-11-10

申请号：US15110701

申请日：2015-01-15

Applicant: EPCOS AG

Inventor： Manfred Schweinzger ,  Stefan Obermair ,  Pavol Dudesek

IPC: H02H3/20

CPC classification number: H02H3/20 ,  H01T4/12

Abstract: An overvoltage protection element and a method for producing an overvoltage protection element is disclosed. In an embodiment, the overvoltage protection element includes a first electrode, a second electrode and a discharge region arranged between the first electrode and the second electrode, wherein a porous discharge dielectric is arranged in the discharge region, and wherein the overvoltage protection element is configured to discharge a gas in pores of the discharge dielectric and produce an electrically conductive connection between the first electrode and the second electrode.

Abstract translation: 公开了一种过电压保护元件及其制造方法。 在一个实施例中，过电压保护元件包括第一电极，第二电极和布置在第一电极和第二电极之间的放电区域，其中多孔放电电介质布置在放电区域中，并且其中配置过电压保护元件 以在放电电介质的孔中排出气体，并在第一电极和第二电极之间产生导电连接。

公开(公告)号：US20170236634A1

公开(公告)日：2017-08-17

申请号：US15358702

申请日：2016-11-22

Applicant: EPCOS AG

Inventor： Christian Block ,  Pavol Dudesek ,  Thomas Feichtinger ,  Christian Hoffmann ,  Guenter Pudmich

IPC: H01F27/28 ,  H01G4/012 ,  H01G4/228 ,  H01G4/30 ,  H01F27/29 ,  H01F41/04 ,  H01F41/12 ,  H01F27/32 ,  H01C1/14 ,  H01C17/06 ,  H01C7/00 ,  H01C7/10 ,  B32B18/00 ,  B32B37/18 ,  B32B37/06 ,  B32B38/00 ,  H01G4/12

CPC classification number: H01F27/2804 ,  B32B18/00 ,  B32B37/06 ,  B32B37/18 ,  B32B38/0036 ,  B32B38/145 ,  B32B2255/205 ,  B32B2264/101 ,  B32B2264/107 ,  B32B2264/12 ,  B32B2305/77 ,  B32B2305/80 ,  B32B2307/202 ,  B32B2307/204 ,  B32B2307/704 ,  B32B2457/16 ,  C04B2235/6562 ,  C04B2235/6565 ,  C04B2235/6567 ,  C04B2237/341 ,  C04B2237/343 ,  C04B2237/346 ,  C04B2237/348 ,  C04B2237/366 ,  C04B2237/564 ,  C04B2237/62 ,  C04B2237/68 ,  C04B2237/702 ,  C04B2237/704 ,  H01C1/14 ,  H01C7/008 ,  H01C7/10 ,  H01C7/18 ,  H01C17/06 ,  H01F10/20 ,  H01F10/265 ,  H01F17/0013 ,  H01F27/29 ,  H01F27/32 ,  H01F41/041 ,  H01F41/12 ,  H01F2027/2809 ,  H01G4/012 ,  H01G4/12 ,  H01G4/228 ,  H01G4/232 ,  H01G4/30 ,  H01G4/40 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/552 ,  H01L25/16 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H03H2001/0085 ,  H05K1/0306 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/4611 ,  H05K3/4629 ,  H05K3/4688 ,  Y10T428/265 ,  H01L2924/00

Abstract: A film stack made from compacted green films and capable of being sintered to form a ceramic component with monolithic multi-layer structure is disclosed. The film stack includes a functional layer comprising a green film comprising a functional ceramic and a tension layer comprising a green film comprising a dielectric material. The tension layer is directly adjacent to the functional layer in the multi-layer structure. The multilayer structure also includes a first metallization plane and second metallization plane. The functional layer is between the first metallization plane and the second metallization plane.

公开(公告)号：US20170011827A1

公开(公告)日：2017-01-12

申请号：US15113397

申请日：2015-01-02

Applicant: EPCOS AG

Inventor： Yasuharu Miyauchi ,  Pavol Dudesek ,  Christian Faistauer ,  Gerhard Fuchs ,  Stefan Obermair ,  Klaus-Dieter Aichholzer ,  Christian Block ,  Sebastian Brunner

IPC: H01C7/12 ,  C03C3/089 ,  H01C7/10 ,  H01C7/18 ,  H01C17/28

CPC classification number: H01C7/12 ,  C03C3/089 ,  H01C7/1006 ,  H01C7/112 ,  H01C7/18 ,  H01C17/285 ,  H01L25/167 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A chip and a method for manufacturing a chip are disclosed. In an embodiment, the chip includes a varistor layer composed of zinc oxide, a multilayered electrode structure which realizes a varistor function in the varistor layer and at least two solderable or bondable external contacts on a first main surface of the varistor layer. The chip further includes a glass layer disposed on the first main surface leaving only the external contacts uncovered, wherein the glass layer includes, as main constituents, oxides of Si and/or Ge, B and K, which in total have at least 70% by weight of the constituents of the glass layer, and wherein the glass layer is substantially free of Al, Ga, Cr and Ti.

Abstract translation: 公开了一种芯片和芯片的制造方法。 在一个实施例中，芯片包括由氧化锌组成的可变电阻层，在压敏电阻层中实现变阻器功能的多层电极结构以及可变阻抗层的第一主表面上的至少两个可焊接或可接合的外部触点。 芯片还包括设置在第一主表面上的玻璃层，仅留下未覆盖的外部触点，其中玻璃层主要包括Si和/或Ge，B和K的氧化物，其总共具有至少70％ 的玻璃层的成分，并且其中玻璃层基本上不含Al，Ga，Cr和Ti。