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公开(公告)号：US20150243865A1
公开(公告)日：2015-08-27
申请号：US14422673
申请日：2013-07-22
Applicant: EPCOS AG
Inventor： Thomas Feichtinger , Sebastian Brunner , Oliver Dernovsek , Klaus-Dieter Aichholzer , Georg Krenn , Axel Pecina , Christian Faistauer
IPC: H01L33/64
CPC classification number: H01L33/644 , H01L33/642 , H01L33/647
Abstract: A light-emitting diode device has a first carrier and at least one light-emitting diode chip, which is arranged on the first carrier. The first carrier has at least one first and one second carrier part, wherein the light-emitting diode chip rests only on the first carrier part. Furthermore, the first and second carrier parts each have a thermal conductivity. The thermal conductivity of the first carrier part is at least 1.5 times the thermal conductivity of the second carrier part. The first carrier part is surrounded laterally by the second carrier part.
Abstract translation: 发光二极管装置具有第一载体和布置在第一载体上的至少一个发光二极管芯片。 第一载体具有至少一个第一和第二载体部分，其中发光二极管芯片仅在第一载体部分上。 此外，第一和第二载体部分各自具有导热性。 第一载体部分的热导率为第二载体部分的热导率的至少1.5倍。 第一载体部分被第二载体部分横向包围。
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公开(公告)号：US11239010B2
公开(公告)日：2022-02-01
申请号：US16061801
申请日：2016-10-18
Applicant: EPCOS AG
Inventor： Christian Faistauer , Klaus-Dieter Aichholzer , Sebastian Brunner , Edmund Payr , Günter Pudmich
Abstract: A mechanically stable main body having a cutout, into which an ESD protection element is at least partly embedded and mechanically fixed by means of a connection means. Electrical terminals of the protection element are connected to terminal pads on the top side of the main body by way of a structured metallic layer bearing on main body and protection element.
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公开(公告)号：US09449958B2
公开(公告)日：2016-09-20
申请号：US14403143
申请日：2013-04-17
Applicant: EPCOS AG
Inventor： Thomas Feichtinger , Oliver Dernovsek , Klaus-Dieter Aichholzer , Sebastian Brunner
CPC classification number: H01L27/0248 , H01L25/167 , H01L33/48 , H01L33/486 , H01L33/62 , H01L33/642 , H01L33/647 , H01L2924/0002 , H01L2924/00
Abstract: A light-emitting diode device includes a carrier having at least one cavity, a light-emitting diode chip is arranged in a manner at least partly recessed in the at least one cavity, and an ESD protection element, which is formed by a partial region of the carrier. Furthermore, a light-emitting diode device includes a carrier having at least one cavity, a light-emitting diode chip arranged on the carrier, and an electrical component arranged at least partly recessed in the at least one cavity. Furthermore, the light-emitting diode device includes an ESD protection element, which is formed by a partial region of the carrier.
Abstract translation: 一种发光二极管器件包括具有至少一个空腔的载体，发光二极管芯片以至少部分地凹入至少一个空腔中的方式布置，并且ESD保护元件由部分区域 的承运人。 此外，发光二极管装置包括具有至少一个空腔的载体，布置在载体上的发光二极管芯片以及至少部分地凹入至少一个空腔中的电气部件。 此外，发光二极管装置包括由载体的部分区域形成的ESD保护元件。
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公开(公告)号：US20190013120A1
公开(公告)日：2019-01-10
申请号：US16061801
申请日：2016-10-18
Applicant: EPCOS AG
Inventor： Christian Faistauer , Klaus-Dieter Aichholzer , Sebastian Brunner , Edmund Payr , Günter Pudmich
Abstract: A mechanically stable main body having a cutout, into which an ESD protection element is at least partly embedded and mechanically fixed by means of a connection means. Electrical terminals of the protection element are connected to terminal pads on the top side of the main body by way of a structured metallic layer bearing on main body and protection element.
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Patent Agency Ranking
公开(公告)号：US09865381B2
公开(公告)日：2018-01-09
申请号：US15113397
申请日：2015-01-02
Applicant: EPCOS AG
Inventor： Yasuharu Miyauchi , Pavol Dudesek , Christian Faistauer , Gerhard Fuchs , Stefan Obermair , Klaus-Dieter Aichholzer , Christian Block , Sebastian Brunner
CPC classification number: H01C7/12 , C03C3/089 , H01C7/1006 , H01C7/112 , H01C7/18 , H01C17/285 , H01L25/167 , H01L2924/0002 , H01L2924/00
Abstract: A chip and a method for manufacturing a chip are disclosed. In an embodiment, the chip includes a varistor layer composed of zinc oxide, a multilayered electrode structure which realizes a varistor function in the varistor layer and at least two solderable or bondable external contacts on a first main surface of the varistor layer. The chip further includes a glass layer disposed on the first main surface leaving only the external contacts uncovered, wherein the glass layer includes, as main constituents, oxides of Si and/or Ge, B and K, which in total have at least 70% by weight of the constituents of the glass layer, and wherein the glass layer is substantially free of Al, Ga, Cr and Ti.
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公开(公告)号：US09418980B2
公开(公告)日：2016-08-16
申请号：US14403143
申请日：2013-04-17
Applicant: EPCOS AG
Inventor： Thomas Feichtinger , Oliver Dernovsek , Klaus-Dieter Aichholzer , Sebastian Brunner
Abstract: A light-emitting diode device includes a carrier having at least one cavity, a light-emitting diode chip is arranged in a manner at least partly recessed in the at least one cavity, and an ESD protection element, which is formed by a partial region of the carrier. Furthermore, a light-emitting diode device includes a carrier having at least one cavity, a light-emitting diode chip arranged on the carrier, and an electrical component arranged at least partly recessed in the at least one cavity. Furthermore, the light-emitting diode device includes an ESD protection element, which is formed by a partial region of the carrier.
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公开(公告)号：US09337408B2
公开(公告)日：2016-05-10
申请号：US14422673
申请日：2013-07-22
Applicant: EPCOS AG
Inventor： Thomas Feichtinger , Sebastian Brunner , Oliver Dernovsek , Klaus-Dieter Aichholzer , Georg Krenn , Axel Pecina , Christian Faistauer
IPC: H01L33/64
CPC classification number: H01L33/644 , H01L33/642 , H01L33/647
Abstract: A light-emitting diode device has a first carrier and at least one light-emitting diode chip, which is arranged on the first carrier. The first carrier has at least one first and one second carrier part, wherein the light-emitting diode chip rests only on the first carrier part. Furthermore, the first and second carrier parts each have a thermal conductivity. The thermal conductivity of the first carrier part is at least 1.5 times the thermal conductivity of the second carrier part. The first carrier part is surrounded laterally by the second carrier part.
Abstract translation: 发光二极管装置具有第一载体和布置在第一载体上的至少一个发光二极管芯片。 第一载体具有至少一个第一和第二载体部分，其中发光二极管芯片仅在第一载体部分上。 此外，第一和第二载体部分各自具有导热性。 第一载体部分的热导率为第二载体部分的热导率的至少1.5倍。 第一载体部分被第二载体部分横向包围。
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公开(公告)号：US20150144983A1
公开(公告)日：2015-05-28
申请号：US14403143
申请日：2013-04-17
Applicant: EPCOS AG
Inventor： Thomas Feichtinger , Oliver Dernovsek , Klaus-Dieter Aichholzer , Sebastian Brunner
CPC classification number: H01L27/0248 , H01L25/167 , H01L33/48 , H01L33/486 , H01L33/62 , H01L33/642 , H01L33/647 , H01L2924/0002 , H01L2924/00
Abstract: A light-emitting diode device includes a carrier having at least one cavity, a light-emitting diode chip is arranged in a manner at least partly recessed in the at least one cavity, and an ESD protection element, which is formed by a partial region of the carrier. Furthermore, a light-emitting diode device includes a carrier having at least one cavity, a light-emitting diode chip, arranged on the carrier, and an electrical component arranged at least partly recessed in the at least one cavity. Furthermore, the light-emitting diode device includes an ESD protection element, which is formed by a partial region of the carrier.
Abstract translation: 一种发光二极管器件包括具有至少一个空腔的载体，发光二极管芯片以至少部分地凹入至少一个空腔中的方式布置，并且ESD保护元件由部分区域 的承运人。 此外，发光二极管器件包括具有至少一个空腔的载体，布置在载体上的发光二极管芯片，以及至少部分地凹入至少一个空腔中的电气部件。 此外，发光二极管装置包括由载体的部分区域形成的ESD保护元件。
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公开(公告)号：US20170011827A1
公开(公告)日：2017-01-12
申请号：US15113397
申请日：2015-01-02
Applicant: EPCOS AG
Inventor： Yasuharu Miyauchi , Pavol Dudesek , Christian Faistauer , Gerhard Fuchs , Stefan Obermair , Klaus-Dieter Aichholzer , Christian Block , Sebastian Brunner
CPC classification number: H01C7/12 , C03C3/089 , H01C7/1006 , H01C7/112 , H01C7/18 , H01C17/285 , H01L25/167 , H01L2924/0002 , H01L2924/00
Abstract: A chip and a method for manufacturing a chip are disclosed. In an embodiment, the chip includes a varistor layer composed of zinc oxide, a multilayered electrode structure which realizes a varistor function in the varistor layer and at least two solderable or bondable external contacts on a first main surface of the varistor layer. The chip further includes a glass layer disposed on the first main surface leaving only the external contacts uncovered, wherein the glass layer includes, as main constituents, oxides of Si and/or Ge, B and K, which in total have at least 70% by weight of the constituents of the glass layer, and wherein the glass layer is substantially free of Al, Ga, Cr and Ti.
Abstract translation: 公开了一种芯片和芯片的制造方法。 在一个实施例中，芯片包括由氧化锌组成的可变电阻层，在压敏电阻层中实现变阻器功能的多层电极结构以及可变阻抗层的第一主表面上的至少两个可焊接或可接合的外部触点。 芯片还包括设置在第一主表面上的玻璃层，仅留下未覆盖的外部触点，其中玻璃层主要包括Si和/或Ge，B和K的氧化物，其总共具有至少70％ 的玻璃层的成分，并且其中玻璃层基本上不含Al，Ga，Cr和Ti。
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