公开(公告)号：US20070026579A1

公开(公告)日：2007-02-01

申请号：US11161320

申请日：2005-07-29

申请人： Edward Nowak ,  Jed Rankin ,  William Tonti ,  Richard Williams

发明人： Edward Nowak ,  Jed Rankin ,  William Tonti ,  Richard Williams

IPC分类号： H01L21/84

CPC分类号： H01L27/10 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An eFuse begins with a single crystal silicon-on-insulator (SOI) structure that has a single crystal silicon layer on a first insulator layer. The single crystal silicon layer is patterned into a strip. Before or after the patterning, the single crystal silicon layer is doped with one or more impurities. At least an upper portion of the single crystal silicon layer is then silicided to form a silicided strip. In one embodiment the entire single crystal silicon strip is silicided to create a silicide strip. Second insulator(s) is/are formed on the silicide strip, so as to isolate the silicided strip from surrounding structures. Before or after forming the second insulators, the method forms electrical contacts through the second insulators to ends of the silicided strip. By utilizing a single crystal silicon strip, any form of semiconductor, such as a diode, conductor, insulator, transistor, etc. can form the underlying portion of the fuse structure. The overlying silicide material allows the fuse to act as a conductor in its unprogrammed state. However, contrary to metal or polysilicon based eFuses which only comprise an insulator in the programmed state, when the inventive eFuse is programmed (and the silicide is moved or broken) the underlying semiconductor structure operates as an active semiconductor device.

摘要翻译： eFuse从在第一绝缘体层上具有单晶硅层的单晶硅绝缘体（SOI）结构开始。 将单晶硅层图案化成条带。 在构图之前或之后，单晶硅层掺杂有一种或多种杂质。 至少单晶硅层的上部然后被硅化以形成硅化带。 在一个实施例中，整个单晶硅带被硅化以产生硅化物条。 在硅化物条上形成第二绝缘体，从而将硅化物带与周围结构隔离。 在形成第二绝缘体之前或之后，该方法通过第二绝缘体形成与硅化带的端部的电接触。 通过使用单晶硅条，任何形式的半导体，例如二极管，导体，绝缘体，晶体管等都可以形成熔丝结构的下面部分。 上覆的硅化物材料允许熔丝作为未编程状态的导体。 然而，与仅编程状态的仅包含绝缘体的金属或多晶硅基eFuse相反，当本发明的eFuse被编程（并且硅化物被移动或断开）时，下面的半导体结构作为有源半导体器件工作。

公开(公告)号：US20070029576A1

公开(公告)日：2007-02-08

申请号：US11161439

申请日：2005-08-03

申请人： Edward Nowak ,  Jed Rankin ,  William Tonti

发明人： Edward Nowak ,  Jed Rankin ,  William Tonti

IPC分类号： H01L27/10

CPC分类号： H01L27/10 ,  H01L23/5256 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to a programmable semiconductor device, preferably a FinFET or tri-gate structure, that contains a first contact element, a second contact element, and at least one fin-shaped fusible link region coupled between the first and second contact elements. The second contact element is laterally spaced apart from the first contact element, and the fin-shaped fusible link region has a vertically notched section. A programming current flowing through the fin-shaped fusible link region causes either significant resistance increase or formation of an electric discontinuity in the vertically notched section. Alternatively, the vertically notched section may contain a dielectric material, and application of a programming voltage between a gate electrode overlaying the vertically notched section and one of the contact elements breaks down the dielectric material and allows current flow between the gate electrode and the fin-shaped fusible link region.

摘要翻译： 本发明涉及一种可编程半导体器件，优选地为FinFET或三栅极结构，其包含第一接触元件，第二接触元件以及耦合在第一和第二接触元件之间的至少一个鳍状可熔连接区域。 第二接触元件与第一接触元件横向间隔开，并且鳍状可熔连接区域具有垂直切口部分。 流过翅片状易熔连接区域的编程电流导致垂直切口部分中显着的电阻增加或电中断的形成。 或者，垂直切口部分可以包含电介质材料，并且在覆盖垂直切口部分的栅极电极和其中一个接触元件之间施加编程电压会破坏电介质材料，并允许电流在栅电极和鳍片间电流之间流动， 形易熔连接区域。

公开(公告)号：US20070224743A1

公开(公告)日：2007-09-27

申请号：US11756078

申请日：2007-05-31

申请人： Brent Anderson ,  Edward Nowak ,  Jed Rankin ,  William Clark

发明人： Brent Anderson ,  Edward Nowak ,  Jed Rankin ,  William Clark

IPC分类号： H01L21/84

CPC分类号： H01L29/78606 ,  H01L27/0248 ,  H01L29/42384 ,  H01L29/785

摘要： A fin-type field effect transistor has an insulator layer above a substrate and a fin extending above the insulator layer. The fin has a channel region, and source and drain regions. A gate conductor is positioned over the channel region. The insulator layer includes a heat dissipating structural feature adjacent the fin, and a portion of the gate conductor contacts the heat dissipating structural feature. The heat dissipating structural feature can comprise a recess within the insulator layer or a thermal conductor extending through the insulator layer.

摘要翻译： 翅片型场效应晶体管具有在衬底上方的绝缘体层和在绝缘体层上方延伸的翅片。 鳍片有一个通道区域，以及源极和漏极区域。 栅极导体位于沟道区域的上方。 绝缘体层包括邻近翅片的散热结构特征，并且栅极导体的一部分接触散热结构特征。 散热结构特征可以包括绝缘体层内的凹槽或延伸穿过绝缘体层的热导体。

公开(公告)号：US20070134864A1

公开(公告)日：2007-06-14

申请号：US11671795

申请日：2007-02-06

申请人： Brent Anderson ,  Edward Nowak ,  Jed Rankin

发明人： Brent Anderson ,  Edward Nowak ,  Jed Rankin

IPC分类号： H01L21/8234

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L29/66795 ,  H01L29/66803

摘要： Disclosed is a structure and method for producing a fin-type field effect transistor (FinFET) that has a buried oxide layer over a substrate, at least one first fin structure and at least one second fin structure positioned on the buried oxide layer. First spacers are adjacent the first fin structure and second spacers are adjacent the second fin structure. The first spacers cover a larger portion of the first fin structure when compared to the portion of the second fin structure covered by the second spacers. Those fins that have larger spacers will receive a smaller area of semiconductor doping and those fins that have smaller spacers will receive a larger area of semiconductor doping. Therefore, there is a difference in doping between the first fins and the second fins that is caused by the differently sized spacers. The difference in doping between the first fins and the second fins changes an effective width of the second fins when compared to the first fins.

摘要翻译： 公开了一种用于制造在衬底上具有掩埋氧化层的鳍式场效应晶体管（FinFET）的结构和方法，至少一个第一鳍结构和位于掩埋氧化物层上的至少一个第二鳍结构。 第一间隔件与第一翅片结构相邻，第二间隔件邻近第二翅片结构。 当与由第二间隔物覆盖的第二鳍结构的部分相比时，第一间隔物覆盖第一鳍结构的较大部分。 具有较大间隔物的那些翅片将接收较小的半导体掺杂面积，并且具有较小间隔物的那些翅片将接收更大面积的半导体掺杂。 因此，由不同尺寸的间隔件引起的第一散热片和第二散热片之间的掺杂存在差异。 与第一鳍片相比，第一鳍片和第二鳍片之间的掺杂差异改变了第二鳍片的有效宽度。

公开(公告)号：US20050221543A1

公开(公告)日：2005-10-06

申请号：US11125063

申请日：2005-05-09

申请人： Andres Bryant ,  Meikei Ieong ,  K. Muller ,  Edward Nowak ,  David Fried ,  Jed Rankin

发明人： Andres Bryant ,  Meikei Ieong ,  K. Muller ,  Edward Nowak ,  David Fried ,  Jed Rankin

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L21/00

CPC分类号： H01L29/4908 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/66795 ,  H01L29/785

摘要： Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention uses provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping on of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. In particular, by asymmetrically doping the two gates, the resulting transistor can, with adequate doping of the body, have a threshold voltage in a range that enables low-voltage CMOS operation. For example, a transistor can be created that has a threshold voltage between 0V and 0.5V for nFETs and between 0 and −0.5V for pFETs.

摘要翻译： 因此，本发明提供一种双门控晶体管及其形成方法，其导致改进的器件性能和密度。 本发明的优选实施例提供了具有不对称栅极掺杂的双门控晶体管，其中双栅极中的一个被简并掺杂为n型，另一个为简并p型。 通过掺杂栅极n型和另一种p型，所得器件的阈值电压得到改善。 特别地，通过不对称地掺杂两个栅极，所得到的晶体管可以通过适当掺杂的体，在允许低电压CMOS操作的范围内具有阈值电压。 例如，可以产生对于nFET具有在0V和0.5V之间的阈值电压并且对于pFET而言在0和-0.5V之间的晶体管。

公开(公告)号：US20070254438A1

公开(公告)日：2007-11-01

申请号：US11774663

申请日：2007-07-09

申请人： Andres Bryant ,  Meikei Ieong ,  K. Muller ,  Edward Nowak ,  David Fried ,  Jed Rankin

发明人： Andres Bryant ,  Meikei Ieong ,  K. Muller ,  Edward Nowak ,  David Fried ,  Jed Rankin

IPC分类号： H01L21/336

CPC分类号： H01L29/4908 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/66795 ,  H01L29/785

摘要： A method for forming a transistor. A semiconductor substrate is provided. The semiconductor substrate is patterned to provide a first body edge. A first gate structure of a first fermi level is provided adjacent the first body edge. The semiconductor substrate is patterned to provide a second body edge. The first and second body edges of the semiconductor substrate define a transistor body. A second gate structure of a second fermi level is provided adjacent the second body edge. A substantially uniform dopant concentration density is formed throughout the transistor body.

摘要翻译： 一种形成晶体管的方法。 提供半导体衬底。 图案化半导体衬底以提供第一本体边缘。 在第一身体边缘附近提供第一费米能级的第一门结构。 图案化半导体衬底以提供第二本体边缘。 半导体衬底的第一和第二主体边缘限定晶体管体。 在第二身体边缘附近设置第二费米能级的第二门结构。 在整个晶体管本体中形成基本均匀的掺杂剂浓度密度。

公开(公告)号：US20070194373A1

公开(公告)日：2007-08-23

申请号：US11276274

申请日：2006-02-22

申请人： Brent Anderson ,  Edward Nowak ,  Jed Rankin

发明人： Brent Anderson ,  Edward Nowak ,  Jed Rankin

IPC分类号： H01L29/94

CPC分类号： H01L21/823807 ,  H01L21/823821 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211

摘要： A complementary metal oxide semiconductor (CMOS) structure includes a semiconductor substrate having first mesa having a first ratio of channel effective horizontal surface area to channel effective vertical surface area. The CMOS structure also includes a second mesa having a second ratio of the same surface areas that is greater than the first ratio. A first device having a first polarity uses the first mesa as a channel and benefits from the enhanced vertical crystallographic orientation. A second device having a second polarity different from the first polarity uses the second mesa as a channel and benefits from the enhanced horizontal crystallographic orientation.

摘要翻译： 互补金属氧化物半导体（CMOS）结构包括具有第一台面的半导体衬底，其具有沟道有效水平表面积与沟道有效垂直表面面积的第一比率。 CMOS结构还包括具有大于第一比率的相同表面积的第二比率的第二台面。 具有第一极性的第一器件使用第一台面作为通道，并且受益于增强的垂直结晶取向。 具有与第一极性不同的第二极性的第二装置使用第二台面作为通道，并且受益于增强的水平晶体取向。

公开(公告)号：US20070010049A1

公开(公告)日：2007-01-11

申请号：US11160360

申请日：2005-06-21

申请人： Brent Anderson ,  Edward Nowak ,  Jed Rankin ,  William Clark

发明人： Brent Anderson ,  Edward Nowak ,  Jed Rankin ,  William Clark

IPC分类号： H01L21/8234

CPC分类号： H01L29/78606 ,  H01L27/0248 ,  H01L29/42384 ,  H01L29/785

摘要： A fin-type field effect transistor has an insulator layer above a substrate and a fin extending above the insulator layer. The fin has a channel region, and source and drain regions. A gate conductor is positioned over the channel region. The insulator layer includes a heat dissipating structural feature adjacent the fin, and a portion of the gate conductor contacts the heat dissipating structural feature. The heat dissipating structural feature can comprise a recess within the insulator layer or a thermal conductor extending through the insulator layer.

公开(公告)号：US20060084212A1

公开(公告)日：2006-04-20

申请号：US11200271

申请日：2005-08-09

申请人： Brent Anderson ,  Edward Nowak ,  Jed Rankin

发明人： Brent Anderson ,  Edward Nowak ,  Jed Rankin

IPC分类号： H01L21/8234

CPC分类号： H01L29/785 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

摘要： A planar substrate device integrated with fin field effect transistors (FinFETs) and a method of manufacture comprises a silicon-on-insulator (SOI) wafer comprising a substrate; a buried insulator layer over the substrate; and a semiconductor layer over the buried insulator layer. The structure further comprises a FinFET over the buried insulator layer and a field effect transistor (FET) integrated in the substrate, wherein the FET gate is planar to the FinFET gate. The structure further comprises retrograde well regions configured in the substrate. In one embodiment, the structure further comprises a shallow trench isolation region configured in the substrate.

摘要翻译： 与鳍状场效应晶体管（FinFET）集成的平面基板器件和制造方法包括：包括衬底的绝缘体上硅（SOI）晶片; 衬底上的掩埋绝缘体层; 以及掩埋绝缘体层上的半导体层。 所述结构还包括在所述掩埋绝缘体层上的FinFET和集成在所述衬底中的场效应晶体管（FET），其中所述FET栅极与所述FinFET栅极平面。 该结构还包括在衬底中配置的逆行阱区。 在一个实施例中，该结构还包括在衬底中配置的浅沟槽隔离区域。

公开(公告)号：US20050093074A1

公开(公告)日：2005-05-05

申请号：US10605905

申请日：2003-11-05

申请人： Brent Anderson ,  Edward Nowak ,  Jed Rankin

发明人： Brent Anderson ,  Edward Nowak ,  Jed Rankin

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L29/76

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A FinFET structure and method of forming a FinFET device. The method includes: (a) providing a semiconductor substrate, (b) forming a dielectric layer on a top surface of the substrate; (c) forming a silicon fin on a top surface of the dielectric layer; (d) forming a protective layer on at least one sidewall of the fin; and (e) removing the protective layer from the at least one sidewall in a channel region of the fin. In a second embodiment, the protective layer is converted to a protective spacer.

摘要翻译： FinFET结构和形成FinFET器件的方法。 该方法包括：（a）提供半导体衬底，（b）在衬底的顶表面上形成电介质层; （c）在所述电介质层的顶表面上形成硅鳍片; （d）在翅片的至少一个侧壁上形成保护层; 和（e）在所述翅片的通道区域中从所述至少一个侧壁去除所述保护层。 在第二实施例中，保护层被转换成保护间隔物。