公开(公告)号：US20130189815A1

公开(公告)日：2013-07-25

申请号：US13792395

申请日：2013-03-11

Applicant: Electronics and Telecommunications Research Institute

Inventor： Min Ki RYU ,  Chi Sun Hwang ,  Chun Won Byun ,  Hye Yong Chu ,  Kyoung Ik Cho

IPC: H01L29/66

CPC classification number: H01L29/66742 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/786 ,  H01L29/7869

Abstract: A method of manufacturing a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the channel. The lower transparent layer or the upper transparent layer is formed of a transparent semiconductor layer, which is the same as the channel.

Abstract translation: 一种制造透明晶体管的方法，所述透明晶体管包括形成在所述基板上的基板，源极和漏极，每个具有下透明层，金属层和上透明层的多层结构，在所述源极和漏极之间形成的沟道 电极和与通道对准的栅电极。 下透明层或上透明层由与通道相同的透明半导体层形成。

公开(公告)号：US12118936B2

公开(公告)日：2024-10-15

申请号：US18119635

申请日：2023-03-09

Applicant: Electronics and Telecommunications Research Institute ,  IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)

Inventor： Chun Won Byun ,  Chan Mo Kang ,  Nam Sung Cho ,  Byong Deok Choi ,  Yong Duck Kim

IPC: G09G3/3233 ,  G09G3/20

CPC classification number: G09G3/3233 ,  G09G3/2007 ,  G09G3/2096 ,  G09G2300/0465 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2310/0202 ,  G09G2310/08 ,  G09G2330/028

Abstract: A pixel circuit may comprise: a first transistor having a first terminal connected to a data line and to which a data signal is applied and a gate terminal connected to a scan line and to which a scan signal is applied; a third transistor having a gate terminal connected to a second terminal of the first transistor and a second terminal connected to a light emitting device; a capacitor having a second terminal commonly connected to the second terminal of the first transistor and the gate terminal of the third transistor; and a second transistor having a second terminal commonly connected to a first terminal of the capacitor and a first terminal of the third transistor, a first terminal connected to a first power supply voltage, and a gate terminal connected to an emission line to which an emission signal is applied.

公开(公告)号：US08716035B2

公开(公告)日：2014-05-06

申请号：US14022705

申请日：2013-09-10

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sung Min Yoon ,  Chun Won Byun ,  Shin Hyuk Yang ,  Sang Hee Park ,  Soon Won Jung ,  Seung Youl Kang ,  Chi Sun Hwang ,  Byoung Gon Yu

IPC: H01L51/00

CPC classification number: H01L29/6684 ,  B82Y10/00 ,  G11C11/22 ,  H01L21/28291 ,  H01L27/1159 ,  H01L29/78391

Abstract: Provided are a nonvolatile memory cell and a method of manufacturing the same. The nonvolatile memory cell includes a memory transistor and a driver transistor. The memory transistor includes a semiconductor layer, a buffer layer, an organic ferroelectric layer, and a gate electrode, which are disposed on a substrate. The driver transistor includes the semiconductor layer, the buffer layer, a gate insulating layer, and the gate electrode, which are disposed on the substrate. The memory transistor and the driver transistor are disposed on the same substrate. The nonvolatile memory cell is transparent in a visible light region.

Abstract translation: 提供一种非易失性存储单元及其制造方法。 非易失性存储单元包括存储晶体管和驱动晶体管。 存储晶体管包括设置在基板上的半导体层，缓冲层，有机铁电层和栅极电极。 驱动晶体管包括设置在基板上的半导体层，缓冲层，栅极绝缘层和栅极电极。 存储晶体管和驱动晶体管设置在同一衬底上。 非易失性存储单元在可见光区域是透明的。

公开(公告)号：US08546199B2

公开(公告)日：2013-10-01

申请号：US13792436

申请日：2013-03-11

Applicant: Electronics and Telecommunications Research Institute

Inventor： Min Ki Ryu ,  Chi Sun Hwang ,  Chun Won Byun ,  Hye Yong Chu ,  Kyoung Ik Cho

IPC: H01L21/336

CPC classification number: H01L29/66742 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/786 ,  H01L29/7869

Abstract: A method of manufacturing a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the channel. The lower transparent layer or the upper transparent layer is formed of a transparent semiconductor layer, which is the same as the channel.

公开(公告)号：US08546198B2

公开(公告)日：2013-10-01

申请号：US13792395

申请日：2013-03-11

Applicant: Electronics and Telecommunications Research Institute

Inventor： Min Ki Ryu ,  Chi Sun Hwang ,  Chun Won Byun ,  Hye Yong Chu ,  Kyoung Ik Cho

IPC: H01L21/336

CPC classification number: H01L29/66742 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/786 ,  H01L29/7869

Abstract: A method of manufacturing a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the channel. The lower transparent layer or the upper transparent layer is formed of a transparent semiconductor layer, which is the same as the channel.

公开(公告)号：US11810522B2

公开(公告)日：2023-11-07

申请号：US17940431

申请日：2022-09-08

Applicant: Electronics and Telecommunications Research Institute ,  IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)

Inventor： Chun Won Byun ,  Chan Mo Kang ,  Nam Sung Cho ,  Byong Deok Choi ,  Yong Duck Kim

IPC: G09G3/3291 ,  G09G3/3233 ,  G09G3/20

CPC classification number: G09G3/3291 ,  G09G3/2018 ,  G09G3/3233 ,  G09G2310/027 ,  G09G2320/0633

Abstract: A pixel circuit driving method of controlling an operation of a light-emitting element provided in a pixel of a display panel may comprise: applying pulse amplitude modulation (PAM) signals having a plurality of levels to a first terminal of a first transistor having a second terminal connected to a control terminal of a second transistor configured to drive the light-emitting element with a current according to a gray scale required for the light-emitting element; and applying a PAM signal of any one level selected from the PAM signals to the control terminal of the second transistor during each sub-frame time corresponding to a turn-on time of the first transistor controlled by a pulse width modulation (PWM) signal having a plurality of sub-frames in a single frame according to the gray scale.