公开(公告)号：US20160248426A1

公开(公告)日：2016-08-25

申请号：US15050187

申请日：2016-02-22

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jae-Eun PI ,  Chunwon BYUN ,  OhSang KWON ,  Eunsuk PARK ,  Min Ki RYU ,  Chi-Sun HWANG

IPC: H03K19/0185

CPC classification number: H03K19/018507

Abstract: A level shifter circuit a first transistor connected between a power source terminal of the level shifter circuit and an output terminal of the level shifter circuit, the first transistor being configured to transmit, in response to a first signal and a second signal, a power source voltage applied from the power source terminal to the output terminal, the first signal being received from an input terminal of the level shifter circuit through a first gate of the first transistor, the second signal being received through a second gate of the first transistor, and a second transistor connected between a ground terminal of the level shifter circuit and the output terminal, the second transistor being configured to transmit a ground voltage from the ground terminal to the output terminal in response to a gate signal received through a gate of the second transistor.

Abstract translation: 电平移位器电路，连接在电平移位器电路的电源端和电平移位器电路的输出端之间的第一晶体管，第一晶体管被配置为响应于第一信号和第二信号，发送电源 从电源端子施加到输出端子的电压，第一信号通过第一晶体管的第一栅极从电平移位器电路的输入端子接收，第二信号通过第一晶体管的第二栅极接收，以及 连接在电平移位器电路的接地端子和输出端子之间的第二晶体管，第二晶体管被配置为响应于通过第二晶体管的栅极接收的栅极信号将接地电压从接地端子传输到输出端子 。

公开(公告)号：US20130189815A1

公开(公告)日：2013-07-25

申请号：US13792395

申请日：2013-03-11

Applicant: Electronics and Telecommunications Research Institute

Inventor： Min Ki RYU ,  Chi Sun Hwang ,  Chun Won Byun ,  Hye Yong Chu ,  Kyoung Ik Cho

IPC: H01L29/66

CPC classification number: H01L29/66742 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/786 ,  H01L29/7869

Abstract: A method of manufacturing a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the channel. The lower transparent layer or the upper transparent layer is formed of a transparent semiconductor layer, which is the same as the channel.

Abstract translation: 一种制造透明晶体管的方法，所述透明晶体管包括形成在所述基板上的基板，源极和漏极，每个具有下透明层，金属层和上透明层的多层结构，在所述源极和漏极之间形成的沟道 电极和与通道对准的栅电极。 下透明层或上透明层由与通道相同的透明半导体层形成。

公开(公告)号：US20160240563A1

公开(公告)日：2016-08-18

申请号：US15043402

申请日：2016-02-12

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE ,  Korea Advanced Institute of Science and Technology

Inventor： Sang-Hee PARK ,  Chi-Sun HWANG ,  Min Ki RYU ,  Jae-Eun PI ,  Jong-Beom KO ,  Hyein YEOM

IPC: H01L27/12 ,  H01L21/027 ,  H01L29/423 ,  H01L21/306 ,  H01L29/786 ,  H01L29/417

CPC classification number: H01L27/1225 ,  H01L21/0274 ,  H01L21/467 ,  H01L27/127 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: Provided is a semiconductor device. The semiconductor device includes a second semiconductor pattern disposed on the substrate and configured to provide a channel region, and a first semiconductor pattern disposed between the substrate and the second semiconductor pattern, wherein the first semiconductor pattern includes a channel region that is a portion in contact with the second semiconductor pattern and source/drain regions that are portions exposed by the second semiconductor pattern.

Abstract translation: 提供一种半导体器件。 所述半导体器件包括设置在所述衬底上并被配置为提供沟道区的第二半导体图案，以及设置在所述衬底和所述第二半导体图案之间的第一半导体图案，其中所述第一半导体图案包括作为接触部分的沟道区 其中第二半导体图案和源极/漏极区域是由第二半导体图案暴露的部分。

公开(公告)号：US20140062572A1

公开(公告)日：2014-03-06

申请号：US14010579

申请日：2013-08-27

Applicant: Electronics and Telecommunications Research Institute ,  Konkuk University Industrial Cooperation Corp.

Inventor： Jae-Eun PI ,  Kee-Chan PARK ,  Sangyeon KIM ,  Joondong KIM ,  Yeon Kyung KIM ,  HongKyun LYM ,  Sang-Hee PARK ,  Byoung Gon YU ,  Chi-Sun HWANG ,  Jong Woo KIM ,  OhSang KWON ,  Min Ki RYU

IPC: H03K17/30

CPC classification number: H03K17/302 ,  H03K19/0185

Abstract: Provided is a single input level shifter. The single input level shifter includes: an input unit applying a power voltage to a first node in response to an input signal and applying the input signal to a second node in response to a reference signal; a bootstrapping unit applying the power voltage to the second node according to a voltage level of the first node; and an output unit applying the input signal to an output terminal in response to the reference signal and applying the power voltage to the output terminal according to the voltage level of the first node, wherein the bootstrapping unit includes a capacitor between the first and second nodes, and when the input signal is shifted from a first voltage level to a second voltage level, the bootstrapping unit raises the voltage level of the first node to a level higher than the power voltage.

Abstract translation: 提供单个输入电平移位器。 单输入电平移位器包括：输入单元，响应于输入信号向第一节点施加电源电压，并响应于参考信号将输入信号施加到第二节点; 引导单元，根据第一节点的电压电平向第二节点施加电源电压; 以及输出单元，其响应于所述参考信号将输入信号施加到输出端子，并且根据所述第一节点的电压电平将所述电源电压施加到所述输出端子，其中所述自举单元包括所述第一和第二节点之间的电容器 并且当所述输入信号从第一电压电平偏移到第二电压电平时，所述自举单元将所述第一节点的电压电平升高到高于所述电源电压的电平。

公开(公告)号：US20130189816A1

公开(公告)日：2013-07-25

申请号：US13792436

申请日：2013-03-11

Applicant: Electronics and Telecommunications Research Institute

Inventor： Min Ki RYU ,  Chi Sun HWANG ,  Chun Won BYUN ,  Hye Yong CHU ,  Kyoung Ik CHO

IPC: H01L29/786

CPC classification number: H01L29/66742 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/786 ,  H01L29/7869

Abstract: A method of manufacturing a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the channel. The lower transparent layer or the upper transparent layer is formed of a transparent semiconductor layer, which is the same as the channel.

公开(公告)号：US20150171833A1

公开(公告)日：2015-06-18

申请号：US14335242

申请日：2014-07-18

Applicant: Konkuk University Industrial Cooperation Corp ,  Electronics and Telecommunications Research Institute

Inventor： Jae-Eun PI ,  Sang-Hee PARK ,  Min Ki RYU ,  Chi-Sun HWANG ,  OhSang KWON ,  Eunsuk PARK ,  Kee-Chan PARK ,  YeonKyung KIM

IPC: H03K3/012 ,  H03K5/01

CPC classification number: H03K3/012 ,  H03K4/026 ,  H03K5/01 ,  H03K5/05

Abstract: Provided is a gate driver circuit. The gate driver circuit includes a plurality of sequentially connected stages, and each of stages includes an input unit including two input transistors forming diode connection, a pull-up unit including a pull-up transistor and a bootstrap capacitor, and first and second pull-down units each including two transistors. According to embodiments, an input capacitor is further included which is connected to a node between the input unit and the pull-up unit. In addition, a carry unit is further included which is connected to an output terminal and formed to transmit an output signal in a high state or a low state to a next stage.

Abstract translation: 提供了一个栅极驱动电路。 栅极驱动器电路包括多个顺序连接的级，并且每个级包括一个输入单元，该输入单元包括形成二极管连接的两个输入晶体管，一个包括上拉晶体管和自举电容器的上拉单元，以及第一和第二上拉电路， 每个下降单元包括两个晶体管。 根据实施例，还包括输入电容器，其连接到输入单元和上拉单元之间的节点。 此外，还包括进位单元，其连接到输出端子并且被形成为将处于高状态或低状态的输出信号传输到下一级。

公开(公告)号：US20140159036A1

公开(公告)日：2014-06-12

申请号：US14020498

申请日：2013-09-06

Applicant: Electronics and Telecommunications Research Institute

Inventor： Su Jae LEE ,  Chi-Sun HWANG ,  Hye Yong CHU ,  Sang Chul LIM ,  Jae-Eun PI ,  Min Ki RYU

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L29/66969 ,  H01L29/78696

Abstract: According to example embodiments of the inventive concept, provided is a transistor with a nano-layered oxide semiconductor layer. The oxide semiconductor layer may include at least one first nano layer and at least one second nano layer that are alternatingly stacked one on another. Here, the first nano layer and the second nano layer may include different materials from each other, and thus, a channel with high electron mobility may be formed at the interface between the first and second nano layers. Accordingly, the transistor can have high reliability.

Abstract translation: 根据本发明构思的示例性实施例，提供了具有纳米层氧化物半导体层的晶体管。 氧化物半导体层可以包括交替堆叠在一起的至少一个第一纳米层和至少一个第二纳米层。 这里，第一纳米层和第二纳米层可以包括彼此不同的材料，因此，可以在第一和第二纳米层之间的界面处形成具有高电子迁移率的沟道。 因此，晶体管可以具有高的可靠性。