中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

8 records (took 0.014 seconds)

    Level shifter circuit
    3.
    发明授权
    Level shifter circuit 有权

    公开(公告)号：US09628079B2

    公开(公告)日：2017-04-18

    申请号：US15050187

    申请日：2016-02-22

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Jae-Eun Pi ,  Chunwon Byun ,  OhSang Kwon ,  Eunsuk Park ,  Min Ki Ryu ,  Chi-Sun Hwang

    IPC: H03K3/01 ,  H03K19/0185

    CPC classification number: H03K19/018507

    Abstract: A level shifter circuit a first transistor connected between a power source terminal of the level shifter circuit and an output terminal of the level shifter circuit, the first transistor being configured to transmit, in response to a first signal and a second signal, a power source voltage applied from the power source terminal to the output terminal, the first signal being received from an input terminal of the level shifter circuit through a first gate of the first transistor, the second signal being received through a second gate of the first transistor, and a second transistor connected between a ground terminal of the level shifter circuit and the output terminal, the second transistor being configured to transmit a ground voltage from the ground terminal to the output terminal in response to a gate signal received through a gate of the second transistor.

    Method for manufacturing oxide thin film transistor
    4.
    发明授权
    Method for manufacturing oxide thin film transistor 有权
    氧化物薄膜晶体管的制造方法

    公开(公告)号：US08841665B2

    公开(公告)日：2014-09-23

    申请号：US13849111

    申请日：2013-03-22

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Sang Hee Park ,  Min Ki Ryu ,  Him Chan Oh ,  Chi Sun Hwang

    IPC: H01L21/16 ,  H01L21/76 ,  H01L21/00 ,  H01L29/786 ,  H01L29/66

    CPC classification number: H01L29/7869 ,  H01L29/66742

    Abstract: Disclosed is a method for manufacturing an oxide thin film transistor, including: forming a gate electrode on a substrate on which a buffer layer is formed; forming a gate insulation layer on an entire surface of the substrate on which the gate electrode is formed; forming an oxide semiconductor layer on the gate insulation layer; forming a first etch stop layer on the oxide semiconductor layer; forming a second etch stop layer on the first etch stop layer by an atomic layer deposition method; patterning the first etch stop layer and the second etch stop layer, or forming a contact hole, through which a part of the oxide semiconductor layer is exposed, in the first etch stop layer and the second etch stop layer; forming a source electrode and a drain electrode on the first etch stop layer and the second etch stop layer; and forming a passivation layer on the entire surface of the substrate on which the source electrode and the drain electrode are formed.

    Abstract translation: 公开了一种制造氧化物薄膜晶体管的方法，包括：在其上形成有缓冲层的基板上形成栅电极; 在其上形成有栅电极的基板的整个表面上形成栅极绝缘层; 在所述栅极绝缘层上形成氧化物半导体层; 在所述氧化物半导体层上形成第一蚀刻停止层; 通过原子层沉积法在第一蚀刻停止层上形成第二蚀刻停止层; 在第一蚀刻停止层和第二蚀刻停止层中形成第一蚀刻停止层和第二蚀刻停止层，或形成暴露氧化物半导体层的一部分的接触孔; 在所述第一蚀刻停止层和所述第二蚀刻停止层上形成源电极和漏电极; 以及在其上形成有源电极和漏电极的基板的整个表面上形成钝化层。

    METHOD FOR MANUFACTURING OXIDE THIN FILM TRANSISTOR
    6.
    发明申请
    METHOD FOR MANUFACTURING OXIDE THIN FILM TRANSISTOR 有权
    制造氧化物薄膜晶体管的方法

    公开(公告)号：US20130264564A1

    公开(公告)日：2013-10-10

    申请号：US13849111

    申请日：2013-03-22

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Sang Hee Park ,  Min Ki Ryu ,  Him Chan Oh ,  Chi Sun Hwang

    IPC: H01L29/786 ,  H01L29/66

    CPC classification number: H01L29/7869 ,  H01L29/66742

    Abstract: Disclosed is a method for manufacturing an oxide thin film transistor, including: forming a gate electrode on a substrate on which a buffer layer is formed; forming a gate insulation layer on an entire surface of the substrate on which the gate electrode is formed; forming an oxide semiconductor layer on the gate insulation layer; forming a first etch stop layer on the oxide semiconductor layer; forming a second etch stop layer on the first etch stop layer by an atomic layer deposition method; patterning the first etch stop layer and the second etch stop layer, or forming a contact hole, through which a part of the oxide semiconductor layer is exposed, in the first etch stop layer and the second etch stop layer; forming a source electrode and a drain electrode on the first etch stop layer and the second etch stop layer; and forming a passivation layer on the entire surface of the substrate on which the source electrode and the drain electrode are formed.

    Abstract translation: 公开了一种制造氧化物薄膜晶体管的方法，包括：在其上形成有缓冲层的基板上形成栅电极; 在其上形成有栅电极的基板的整个表面上形成栅极绝缘层; 在所述栅极绝缘层上形成氧化物半导体层; 在所述氧化物半导体层上形成第一蚀刻停止层; 通过原子层沉积法在第一蚀刻停止层上形成第二蚀刻停止层; 在第一蚀刻停止层和第二蚀刻停止层中形成第一蚀刻停止层和第二蚀刻停止层，或形成暴露氧化物半导体层的一部分的接触孔; 在所述第一蚀刻停止层和所述第二蚀刻停止层上形成源电极和漏电极; 以及在其上形成有源电极和漏电极的基板的整个表面上形成钝化层。

    Oxide transistor with nano-layered structure
    7.
    发明授权
    Oxide transistor with nano-layered structure 有权
    具有纳米级结构的氧化物晶体管

    公开(公告)号：US09263592B2

    公开(公告)日：2016-02-16

    申请号：US14020498

    申请日：2013-09-06

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Su Jae Lee ,  Chi-Sun Hwang ,  Hye Yong Chu ,  Sang Chul Lim ,  Jae-Eun Pi ,  Min Ki Ryu

    IPC: H01L29/786 ,  H01L29/66 ,  H01L21/02

    CPC classification number: H01L29/7869 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L29/66969 ,  H01L29/78696

    Abstract: A transistor includes source/drain electrodes provided on a substrate; a semiconductor oxide layer provided between the source/drain electrodes; a gate electrode facing the semiconductor oxide layer; and a gate insulating layer interposed between the semiconductor oxide layer and the gate electrode, wherein the semiconductor oxide layer has a nano-layered structure including at least one first nano layer comprised of a first material and at least one second nano layer comprised of a second material that are alternatingly stacked one on another to provide at least one interface, and wherein the first material and the second material are different materials that are effective to form an electron transfer channel layer at the interface.

    Abstract translation: 晶体管包括设置在基板上的源/漏电极; 设置在源极/漏极之间的半导体氧化物层; 面对半导体氧化物层的栅电极; 以及插入在所述半导体氧化物层和所述栅电极之间的栅极绝缘层，其中所述半导体氧化物层具有纳米层状结构，所述纳米层结构包括由第一材料构成的至少一个第一纳米层和由第二材料构成的至少一个第二纳米层 交替层叠在一起以提供至少一个界面的材料，并且其中所述第一材料和所述第二材料是在所述界面处有效形成电子传输沟道层的不同材料。

    Single input level shifter
    8.
    发明授权
    Single input level shifter 有权
    单输入电平转换器

    公开(公告)号：US09035688B2

    公开(公告)日：2015-05-19

    申请号：US14010579

    申请日：2013-08-27

    Applicant: Konkuk University Industrial Cooperation Corp. ,  Electronics and Telecommunications Research Institute

    Inventor： Jae-Eun Pi ,  Kee-Chan Park ,  Sangyeon Kim ,  Joondong Kim ,  Yeon Kyung Kim ,  HongKyun Lym ,  Sang-Hee Park ,  Byoung Gon Yu ,  Chi-Sun Hwang ,  Jong Woo Kim ,  OhSang Kwon ,  Min Ki Ryu

    IPC: H03L5/00 ,  H03K17/30 ,  H03K19/0185

    CPC classification number: H03K17/302 ,  H03K19/0185

    Abstract: Provided is a single input level shifter. The single input level shifter includes: an input unit applying a power voltage to a first node in response to an input signal and applying the input signal to a second node in response to a reference signal; a bootstrapping unit applying the power voltage to the second node according to a voltage level of the first node; and an output unit applying the input signal to an output terminal in response to the reference signal and applying the power voltage to the output terminal according to the voltage level of the first node, wherein the bootstrapping unit includes a capacitor between the first and second nodes, and when the input signal is shifted from a first voltage level to a second voltage level, the bootstrapping unit raises the voltage level of the first node to a level higher than the power voltage.

    Abstract translation: 提供单个输入电平移位器。 单输入电平移位器包括：输入单元，响应于输入信号向第一节点施加电源电压，并响应于参考信号将输入信号施加到第二节点; 引导单元，根据第一节点的电压电平向第二节点施加电源电压; 以及输出单元，其响应于所述参考信号将输入信号施加到输出端子，并且根据所述第一节点的电压电平将所述电源电压施加到所述输出端子，其中所述自举单元包括所述第一和第二节点之间的电容器 并且当所述输入信号从第一电压电平偏移到第二电压电平时，所述自举单元将所述第一节点的电压电平升高到高于所述电源电压的电平。

Patent Agency Ranking