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    SRAM device including oxide semiconductor
    2.
    发明授权
    SRAM device including oxide semiconductor 有权

    公开(公告)号：US11895817B2

    公开(公告)日：2024-02-06

    申请号：US17529817

    申请日：2021-11-18

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Sung Haeng Cho ,  Byung-Do Yang ,  Sooji Nam ,  Jaehyun Moon ,  Jae-Eun Pi ,  Jae-Min Kim

    IPC: H10B10/00 ,  G11C11/417 ,  G11C11/412

    CPC classification number: H10B10/12 ,  G11C11/412 ,  G11C11/417

    Abstract: Provided is a static random-access memory (SRAM) device. The SRAM device includes a substrate including a PMOS area, a circuit wiring structure including an insulating layer and a wiring layer alternately stacked on the substrate, wherein the circuit wiring structure includes a first NMOS area and a second NMOS area vertically separated from the PMOS area with the first NMOS area therebetween, a first transistor including a first gate electrode disposed on the PMOS area, source/drain areas formed on the PMOS area on both sides of the first gate electrode, and a first channel connecting the source and drain areas to each other, a second transistor including a second gate electrode disposed in the first NMOS area and a second channel vertically overlapping the second gate electrode, and a third transistor including a third gate electrode disposed in the second NMOS area and a third channel vertically overlapping the third gate electrode, wherein the first channel includes silicon, wherein the second channel and the third channel include an oxide semiconductor.

    Level shifter circuit
    3.
    发明授权
    Level shifter circuit 有权

    公开(公告)号：US09628079B2

    公开(公告)日：2017-04-18

    申请号：US15050187

    申请日：2016-02-22

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Jae-Eun Pi ,  Chunwon Byun ,  OhSang Kwon ,  Eunsuk Park ,  Min Ki Ryu ,  Chi-Sun Hwang

    IPC: H03K3/01 ,  H03K19/0185

    CPC classification number: H03K19/018507

    Abstract: A level shifter circuit a first transistor connected between a power source terminal of the level shifter circuit and an output terminal of the level shifter circuit, the first transistor being configured to transmit, in response to a first signal and a second signal, a power source voltage applied from the power source terminal to the output terminal, the first signal being received from an input terminal of the level shifter circuit through a first gate of the first transistor, the second signal being received through a second gate of the first transistor, and a second transistor connected between a ground terminal of the level shifter circuit and the output terminal, the second transistor being configured to transmit a ground voltage from the ground terminal to the output terminal in response to a gate signal received through a gate of the second transistor.

    HOLOGRAPHIC DISPLAY DEVICE
    4.
    发明申请
    HOLOGRAPHIC DISPLAY DEVICE 审中-公开
    全景显示设备

    公开(公告)号：US20160209809A1

    公开(公告)日：2016-07-21

    申请号：US14994029

    申请日：2016-01-12

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Yong Hae Kim ,  Chi-Sun Hwang ,  Gi Heon Kim ,  Himchan Oh ,  Hojun Ryu ,  Chunwon Byun ,  Myung Lae Lee ,  Jae Won Lee ,  Jae-Eun Pi

    IPC: G03H1/30 ,  G02F1/1335 ,  G02F1/1343 ,  G03H1/22

    CPC classification number: G03H1/30 ,  G02F1/133553 ,  G02F1/133617 ,  G02F1/134336 ,  G03H1/02 ,  G03H1/2294 ,  G03H2001/0224 ,  G03H2001/2263 ,  G03H2001/303 ,  G03H2225/35 ,  G03H2225/52

    Abstract: Provided is a holographic display device. The holographic display device includes a light source unit configured to emit a light, and a spatial light modulator (SLM) configured to modulate at least one of a phase and amplitude of the light emitted from the light source unit to output a hologram image, and including a plurality of pixel groups that are arranged in a first direction, wherein each of the plurality of pixel groups includes: first pixels arranged in a matrix x1×y1 and providing an image having a first wavelength, and second pixels adjacent to the first pixels in the first direction, arranged in a matrix x2×y2, and providing an image having a second wavelength that is different from the first wavelength.

    Abstract translation: 提供了一种全息显示装置。 全息显示装置包括被配置为发射光的光源单元和被配置为调制从光源单元发射的光的相位和幅度中的至少一个以输出全息图像的空间光调制器（SLM），以及 包括沿第一方向布置的多个像素组，其中所述多个像素组中的每一个包括：以矩阵x 1×y 1排列并提供具有第一波长的图像的第一像素和与所述第一像素相邻的第二像素 在第一方向上以矩阵x2×y2排列，并且提供具有与第一波长不同的第二波长的图像。

    CMOS logic element including oxide semiconductor
    5.
    发明授权
    CMOS logic element including oxide semiconductor 有权

    公开(公告)号：US12237331B2

    公开(公告)日：2025-02-25

    申请号：US17520853

    申请日：2021-11-08

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Sung Haeng Cho ,  Byung-Do Yang ,  Sooji Nam ,  Jaehyun Moon ,  Jae-Eun Pi ,  Jae-Min Kim

    IPC: H01L27/02 ,  H01L27/092 ,  H01L29/24 ,  H03K19/018 ,  H03K19/0185 ,  H03K19/0948

    Abstract: Provided is a Complementary Metal Oxide Semiconductor (CMOS) logic element. The CMOS logic element includes a substrate including a PMOS area, a circuit wiring structure including an insulating layer and a wiring layer alternately stacked on the substrate, wherein the circuit wiring structure includes an NMOS area vertically spaced apart from the PMOS area, a first transistor disposed on the PMOS area, and a second transistor disposed on the NMOS area and complementarily connected to the first transistor, wherein the first transistor includes a first gate electrode, source/drain areas formed on the PMOS area on both sides of the first gate electrode, and a first channel connecting the source and drain areas to each other, wherein the second transistor includes a second gate electrode and a second channel vertically overlapping the second gate electrode, wherein the first channel includes silicon, wherein the second channel includes an oxide semiconductor.

    Fingerprint sensor and electronic device having the same
    9.
    发明授权
    Fingerprint sensor and electronic device having the same 有权

    公开(公告)号：US10068123B2

    公开(公告)日：2018-09-04

    申请号：US15380415

    申请日：2016-12-15

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Jae-Eun Pi

    IPC: G06K9/28 ,  G06K9/00

    Abstract: Provided is a fingerprint sensor. The fingerprint sensor according to an embodiment of the inventive concept includes a plurality of transmission lines, a plurality of receive lines, and a sensor array including sensor units connected to the plurality of transmission lines. Each of the sensor units includes a switch transistor having a gate terminal and one terminal, which are commonly connected to a corresponding transmission line of the plurality of transmission lines and a sensor transistor connected between the other end of the switch transistor and a corresponding receive line of the plurality of receive lines. The sensor transistor performs a current suppression on in response to a voltage of a virtual gate that is touched by a fingerprint.

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