公开(公告)号：US20070130598A1

公开(公告)日：2007-06-07

申请号：US11607637

申请日：2006-11-30

申请人： Eun-A Choi ,  Nae-Soo Kim ,  Dae-Ig Chang ,  Deock-Gil Oh

发明人： Eun-A Choi ,  Nae-Soo Kim ,  Dae-Ig Chang ,  Deock-Gil Oh

IPC分类号： H04N7/173 ,  H04N7/18 ,  H04N7/16 ,  H04N7/20

CPC分类号： H04L12/2803 ,  H04B3/54 ,  H04B2203/5441 ,  H04B2203/5445 ,  H04L12/2801 ,  H04L12/2818 ,  H04L2012/2841 ,  H04L2012/2843 ,  H04N21/4131 ,  H04N21/4227 ,  H04N21/4355 ,  H04N21/43615 ,  H04N21/478 ,  H04N21/6143 ,  H04N21/6193 ,  H04N21/6547

摘要： Provided is a digital satellite broadcasting set-top box and a home network control system employing the same. The set-top box includes: a satellite signal receiving unit for receiving a satellite signal including a home network control signal for controlling the household appliances through a satellite broadcasting network from a remote terminal; and a control unit for extracting a household appliances control signal included in the satellite signal transmitted from the satellite signal receiving unit and commanding a power line converter to transmit the household appliances control signal to a corresponding household appliance, wherein the power line converter converts the household appliances control signal transmitted from the digital satellite broadcasting set-top box into a power line communication signal and transmits the power line communication signal on the home network through a power line.

摘要翻译： 提供了一种数字卫星广播机顶盒和采用其的家庭网络控制系统。 机顶盒包括：卫星信号接收单元，用于通过卫星广播网络从远程终端接收包括用于控制家用电器的家庭网络控制信号的卫星信号; 以及控制单元，用于提取从卫星信号接收单元发送的卫星信号中包含的家用电器控制信号，并指示电力线转换器将家用电器控制信号发送到相应的家用电器，其中电力线转换器将家庭 家用电器控制信号从数字卫星广播机顶盒发送到电力线通信信号，并通过电力线在家庭网络上发送电力线通信信号。

公开(公告)号：US06732326B2

公开(公告)日：2004-05-04

申请号：US09846477

申请日：2001-04-30

申请人： Eun-A Choi ,  Jin-Ho Kim ,  Nae-Soo Kim ,  Deock-Gil Oh

发明人： Eun-A Choi ,  Jin-Ho Kim ,  Nae-Soo Kim ,  Deock-Gil Oh

IPC分类号： H03M1341

CPC分类号： H03M13/6362 ,  H03M13/395 ,  H03M13/3961 ,  H03M13/41 ,  H03M13/4107

摘要： A structure and a method for depuncturing an input bit stream being input to a Viterbi decoder when the Viterbi decoder is designed by using a Radix-4 branch metric calculator in a method for designing the Viterbi decoder that decodes a punctured code at a high-speed, are disclosed. A depuncture structure for Radix-4 branch metric calculation in a high-speed Viterbi decoder includes four FIFOs, four multiplexers, and one Radix-4 branch metric calculator. Two input bit streams of I and Q are connected to two upper FIFOs and two lower FIFOs. An output terminal of FIFO is connected to upper and lower multiplexers of the next stage. One output terminal of each multiplexer is connected to Radix-4 branch metric calculator. As a result, Radix-4 branch metric calculation can be achieved by using the same clock as a clock speed of the input I and Q bit streams. This structure and this method can be applied to a depuncturing process for Radix-4 branch metric calculation of all punctured codes derived from ½ code.

摘要翻译： 在维特比解码器被设计成通过在设计维特比解码器的方法中设计的维特比解码器的结构和方法被输入到维特比解码器，该维特比解码器以高速解码穿孔码 ，被披露。 在高速维特比解码器中用于基数4分支度量计算的解穿孔结构包括四个FIFO，四个多路复用器和一个基数-4分支度量计算器。 I和Q的两个输入比特流连接到两个较高的FIFO和两个较低的FIFO。 FIFO的输出端子连接到下一级的上下复用器。 每个多路复用器的一个输出端连接到基数-4分支度量计算器。 因此，可以通过使用与输入I和Q位流的时钟速度相同的时钟来实现基数-4分支度量计算。 该结构和该方法可以应用于从½码导出的所有穿孔码的基数-4分支度量计算的解穿孔过程。

公开(公告)号：US07539920B2

公开(公告)日：2009-05-26

申请号：US11265451

申请日：2005-11-02

申请人： Eun-A Choi ,  Nae-Soo Kim ,  Deock-Gil Oh ,  Ji-Won Jung

发明人： Eun-A Choi ,  Nae-Soo Kim ,  Deock-Gil Oh ,  Ji-Won Jung

IPC分类号： H03M13/00

CPC分类号： H03M13/11

摘要： Provided are an LDPC decoding apparatus and method using a sequential decoding algorithm having a partial group, capable of reducing the number of an iterative decoding by more than half without degrading the performance and increasing an amount of computation. The LDPC decoding method includes the steps of: receiving a prior probability information (channel values) based on information on channel values associated with distance between symbol signals in constellation related to the received noise and LDPC encoded data, and initializing bit nodes; dividing check nodes into partial groups before updating check node information based on the prior probability information, and performing a decoding by applying a sequential decoding algorithm; determining whether a parity check equations are satisfied; and outputting decoded messages obtained when satisfying the parity check equation or after terminating an iterative processor by a termination algorithm.

摘要翻译： 提供了一种使用具有部分组的顺序解码算法的LDPC解码装置和方法，其能够将迭代解码的数量减少一半以上，而不降低性能并增加计算量。 LDPC解码方法包括以下步骤：基于与接收到的噪声相关的星座中的符号信号与LDPC编码数据之间的距离相关的信道值的信息，以及初始化比特节点，接收先验概率信息（信道值） 在根据先验概率信息更新校验节点信息之前，将校验节点划分为部分组，并通过应用顺序解码算法执行解码; 确定是否满足奇偶校验方程; 并输出在满足奇偶校验方程时获得的解码消息，或者通过终止算法终止迭代处理器。

公开(公告)号：US20070150789A1

公开(公告)日：2007-06-28

申请号：US11607592

申请日：2006-11-30

申请人： Eun-A Choi ,  Dae-Ig Chang ,  Deock-Gil Oh

发明人： Eun-A Choi ,  Dae-Ig Chang ,  Deock-Gil Oh

IPC分类号： H03M13/00

CPC分类号： H03M13/1165 ,  H03M13/1111

摘要： Provided is a low-density parity-check (LDPC) decoding apparatus and method using a type-classified index. The apparatus includes: a memory allocating unit for multiplying reception data by an estimated channel value and storing a multiplied value in a memory including a plurality of memory block; an index storing unit for storing a Read Only Memory (ROM) index, an address index and a permutation index for the stored data; a check node updating unit for bring the stored data in parallel based on the ROM index, the address index, and the permutation index and updating a check node; and a bit node updating unit for updating a bit node based on the data stored in the memory and check node information updated in the check node updating unit.

摘要翻译： 提供了一种使用类型分类索引的低密度奇偶校验（LDPC）解码装置和方法。 该装置包括：存储器分配单元，用于将接收数据乘以估计的信道值，并将乘法值存储在包括多个存储块的存储器中; 索引存储单元，用于存储所存储的数据的只读存储器（ROM）索引，地址索引和置换索引; 检查节点更新单元，用于基于所述ROM索引，所述地址索引和所述置换索引并行存储所述数据，并更新校验节点; 以及位节点更新单元，用于基于存储在存储器中的数据更新位节点，并且校验在校验节点更新单元中更新的节点信息。

公开(公告)号：US08122315B2

公开(公告)日：2012-02-21

申请号：US11607592

申请日：2006-11-30

申请人： Eun-A Choi ,  Dae-Ig Chang ,  Deock-Gil Oh

发明人： Eun-A Choi ,  Dae-Ig Chang ,  Deock-Gil Oh

IPC分类号： H03M13/00

CPC分类号： H03M13/1165 ,  H03M13/1111

摘要： Provided is a low-density parity-check (LDPC) decoding apparatus and method using a type-classified index. The apparatus includes: a memory allocating unit for multiplying reception data by an estimated channel value and storing a multiplied value in a memory including a plurality of memory block; an index storing unit for storing a Read Only Memory (ROM) index, an address index and a permutation index for the stored data; a check node updating unit for bring the stored data in parallel based on the ROM index, the address index, and the permutation index and updating a check node; and a bit node updating unit for updating a bit node based on the data stored in the memory and check node information updated in the check node updating unit.

摘要翻译： 提供了一种使用类型分类索引的低密度奇偶校验（LDPC）解码装置和方法。 该装置包括：存储器分配单元，用于将接收数据乘以估计的信道值，并将乘法值存储在包括多个存储块的存储器中; 索引存储单元，用于存储所存储的数据的只读存储器（ROM）索引，地址索引和置换索引; 检查节点更新单元，用于基于所述ROM索引，所述地址索引和所述置换索引并行存储所述数据，并更新校验节点; 以及位节点更新单元，用于基于存储在存储器中的数据更新位节点，并且校验在校验节点更新单元中更新的节点信息。

公开(公告)号：US20060136799A1

公开(公告)日：2006-06-22

申请号：US11265451

申请日：2005-11-02

申请人： Eun-A Choi ,  Nae-Soo Kim ,  Deock-Gil Oh ,  Ji-Won Jung

发明人： Eun-A Choi ,  Nae-Soo Kim ,  Deock-Gil Oh ,  Ji-Won Jung

IPC分类号： H03M13/00

CPC分类号： H03M13/11

摘要： Provided are an LDPC decoding apparatus and method using a sequential decoding algorithm having a partial group, capable of reducing the number of an iterative decoding by more than half without degrading the performance and increasing an amount of computation. The LDPC decoding method includes the steps of: receiving a prior probability information (channel values) based on information on channel values associated with distance between symbol signals in constellation related to the received noise and LDPC encoded data, and initializing bit nodes; dividing check nodes into partial groups before updating check node information based on the prior probability information, and performing a decoding by applying a sequential decoding algorithm; determining whether a parity check equations are satisfied; and outputting decoded messages obtained when satisfying the parity check equation or after terminating an iterative processor by a termination algorithm.

公开(公告)号：US07010059B2

公开(公告)日：2006-03-07

申请号：US10406094

申请日：2003-04-02

申请人： Yun-Jeong Song ,  Young-Wan Kim ,  Nae-Soo Kim ,  Deock-Gil Oh

发明人： Yun-Jeong Song ,  Young-Wan Kim ,  Nae-Soo Kim ,  Deock-Gil Oh

IPC分类号： H04L27/22

CPC分类号： H04L27/2273 ,  H04L27/3809 ,  H04L2027/0028 ,  H04L2027/0057

摘要： Disclosed is a quadrature demodulator for high-speed wireless communication, which comprises: an A/D converter for converting received signals into digital signals; a signal recovery unit for recovering carriers and symbol timing from the signals converted by the A/D converter; a decision unit for detecting recovered signals output by the signal recovery unit, and performing a decision process on them; an I/Q gain imbalance detector for detecting gain imbalances of the I and Q-phase components from the recovered signals, and outputting an I/Q gain compensation value for compensating for the gain imbalances; and an I/Q gain compensator, provided between the A/D converter and the signal recovery unit, for reflecting the I/Q gain compensation value output by the I/Q gain imbalance detector to the received signals.

摘要翻译： 公开了一种用于高速无线通信的正交解调器，其包括：A / D转换器，用于将接收到的信号转换成数字信号; 信号恢复单元，用于从由A / D转换器转换的信号中恢复载波和符号定时; 判定单元，用于检测由信号恢复单元输出的恢复信号，并对其进行决定处理; I / Q增益不平衡检测器，用于检测来自恢复信号的I相和Q相分量的增益不平衡，并输出用于补偿增益不平衡的I / Q增益补偿值; 以及设置在A / D转换器和信号恢复单元之间的用于将由I / Q增益不平衡检测器输出的I / Q增益补偿值反映到接收信号的I / Q增益补偿器。

公开(公告)号：US08422604B2

公开(公告)日：2013-04-16

申请号：US12518103

申请日：2007-10-30

申请人： Pan-Soo Kim ,  Dae-Ig Chang ,  Deock-Gil Oh ,  Seokheon Kang ,  Deokchang Kang ,  Wonjin Sung

发明人： Pan-Soo Kim ,  Dae-Ig Chang ,  Deock-Gil Oh ,  Seokheon Kang ,  Deokchang Kang ,  Wonjin Sung

IPC分类号： H03D1/00

CPC分类号： H04L27/2656 ,  H04L7/042 ,  H04L27/2675

摘要： Provided is a method for detecting frame sync and frame structure in a satellite broadcasting system, which acquires an estimated value for detecting frame structure and frame sync and overcomes distortion of correlation analysis values by summing differential correlation values for SOF positions in consideration of the variable frame length, and selecting a maximum value in a channel environment with low signal-to-noise ratio and high frequency error. SOF is a sync word indicating the start point of a frame. The method includes the steps of: acquiring SOF differential correlation value sequences; acquiring sums (di,t) of the correlation values normalized for SOF positions based on the number of symbols per frame by using the above-generated SOF differential correlation value sequences; and selecting a maximum value (dz,x) among the sums of correlation values, detecting z as a frame sync position, and detecting x as a frame structure index.

摘要翻译： 提供了一种用于检测卫星广播系统中的帧同步和帧结构的方法，其获取用于检测帧结构和帧同步的估计值，并通过将SOF位置的差分相关值相加考虑到可变帧来克服相关分析值的失真 长度，并在低信噪比和高频误差的信道环境中选择最大值。 SOF是指示帧起始点的同步字。 该方法包括以下步骤：获取SOF差分相关值序列; 通过使用上述生成的SOF差分相关值序列，基于每帧的符号数，获取针对SOF位置归一化的相关值的和（di，t） 并且选择相关值之和中的最大值（dz，x），检测z作为帧同步位置，并且检测x作为帧结构索引。

公开(公告)号：US20100007743A1

公开(公告)日：2010-01-14

申请号：US12518242

申请日：2007-10-31

申请人： Pan-Soo Kim ,  Dae-Ig Chang ,  Deock-Gil Oh ,  Sangtae Kim ,  Seokheon Kang ,  Wonjin Sung

发明人： Pan-Soo Kim ,  Dae-Ig Chang ,  Deock-Gil Oh ,  Sangtae Kim ,  Seokheon Kang ,  Wonjin Sung

IPC分类号： H04N17/00

CPC分类号： H04N21/4382 ,  H04H40/90 ,  H04L7/042 ,  H04L27/2656 ,  H04N7/20 ,  H04N21/238 ,  H04N21/2383 ,  H04N21/242 ,  H04N21/6143

摘要： Provided is a method for detecting frame sync and frame structure in a satellite broadcasting system. The method for detecting frame sync and frame structure includes the steps of: calculating differential correlation values of reception symbols; generating index sequences of reception symbols whose differential correlation values calculated above exceed a threshold value; calculating positions estimated as frame start points which correspond to a total frame number based on the number of symbols per frame for each frame structure; and detecting frame sync and frame structure based on the umber of positions where the above-calculated frame start point estimated positions and the above-generated index sequences are matched.

摘要翻译： 提供了一种用于在卫星广播系统中检测帧同步和帧结构的方法。 用于检测帧同步和帧结构的方法包括以下步骤：计算接收符号的差分相关值; 产生上述计算出的差分相关值的接收符号的索引序列超过阈值; 基于每个帧结构的每个符号的数量，计算估计为与总帧数相对应的帧起始点的位置; 以及基于上述计算出的帧起始点估计位置和上述生成的索引序列匹配的位置的数量来检测帧同步和帧结构。

公开(公告)号：US20080285685A1

公开(公告)日：2008-11-20

申请号：US12096119

申请日：2006-12-07

申请人： Dae-Ig Chang ,  Deock-Gil Oh ,  Kwang-Min Hyun ,  Dong-Weon Yoon ,  Sang-Kyu Park

发明人： Dae-Ig Chang ,  Deock-Gil Oh ,  Kwang-Min Hyun ,  Dong-Weon Yoon ,  Sang-Kyu Park

IPC分类号： H04L27/38

CPC分类号： H04L25/067 ,  H04L1/005 ,  H04L27/38

摘要： Provided are an apparatus and method for generating a soft bit metric and a multi-level (M-ary) Quadrature Amplitude Modulation (QAM) receiving system using the same. The apparatus includes an analog to digital converter for converting an analog symbol signal of a demodulated I (Inphase) or Q (Quadrature) channel into a digital signal, a sealer for scaling the converted digital signal based on a reference value used for determining a space between symbols, a positive integer converter for calculating a positive integer of the scaled digital I or Q channel symbol signal, a sign determinator for determining a sign of the scaled digital I or Q channel symbol signal, and a bit information converter for converting the scaled digital I or Q channel symbol signal into soft bit metric information per bit on the basis of the calculated positive integer and the determined sign value.

摘要翻译： 提供了一种用于生成软比特度量的装置和方法以及使用其的多级（M元）正交幅度调制（QAM）正交调制（QAM）接收系统。 该装置包括用于将解调的I（同相）或Q（正交）信道的模拟符号信号转换为数字信号的模数转换器，用于基于用于确定空间的参考值缩放转换的数字信号的缩放器 在符号之间，用于计算缩放的数字I或Q信道符号信号的正整数的正整数转换器，用于确定缩放的数字I或Q信道符号信号的符号的符号确定器，以及用于将缩放的 基于计算的正整数和确定的符号值，将数字I或Q通道符号信号转换为每位的软比特度量信息。