摘要:
Disclosed is a quadrature demodulator for high-speed wireless communication, which comprises: an A/D converter for converting received signals into digital signals; a signal recovery unit for recovering carriers and symbol timing from the signals converted by the A/D converter; a decision unit for detecting recovered signals output by the signal recovery unit, and performing a decision process on them; an I/Q gain imbalance detector for detecting gain imbalances of the I and Q-phase components from the recovered signals, and outputting an I/Q gain compensation value for compensating for the gain imbalances; and an I/Q gain compensator, provided between the A/D converter and the signal recovery unit, for reflecting the I/Q gain compensation value output by the I/Q gain imbalance detector to the received signals.
摘要:
The present invention provides an apparatus for compensating a phase difference of a receiver, the apparatus including: an accumulating unit for accumulating a radio frequency (RF) input signal and generating an accumulated RF signal in order to minimize an effect of a background noise of the RF input signal; a early-local oscillating unit for generating a phase-early local oscillated signal based on a local oscillated signal of the receiver; a late-local oscillating unit for generating a phase-late local oscillated signal based on a local oscillated signal of the receiver; a phase early-late compensating unit for compensating a phase early-late based on the accumulated RF input signal and the phase-early and phase-late local oscillated signals; a look-up table data mapping unit for controlling a phase of the local oscillated signal with respect to a phase difference; and a feedback transmitting unit for transmitting a phase compensating data to the local oscillator.
摘要:
The present invention provides an apparatus for compensating a phase difference of a receiver, the apparatus including: an accumulating unit for accumulating a radio frequency (RF) input signal and generating an accumulated RF signal in order to minimize an effect of a background noise of the RF input signal; a early-local oscillating unit for generating a phase-early local oscillated signal based on a local oscillated signal of the receiver; a late-local oscillating unit for generating a phase-late local oscillated signal based on a local oscillated signal of the receiver; a phase early-late compensating unit for compensating a phase early-late based on the accumulated RF input signal and the phase-early and phase-late local oscillated signals; a look-up table data mapping unit for controlling a phase of the local oscillated signal with respect to a phase difference; and a feedback transmitting unit for transmitting a phase compensating data to the local oscillator.
摘要:
Disclosed is a method for detecting and correcting amplitude and phase imbalances between in-phase (I) and quadrature-phase (Q) components in a high-speed wireless communication quadrature demodulator, which comprises: a) comparing an input signal with a signal determined by a quadrant to which the input signal belongs, and detecting imbalances between I and Q components with respect to the input signal; and b) using the imbalances detected in a) to correct the input signal. The present invention prevents distorting of the demodulator's performance caused by the imbalances to between I and Q components and increases application to high-speed wireless communication.
摘要:
Provided are an LDPC decoding apparatus and method using a sequential decoding algorithm having a partial group, capable of reducing the number of an iterative decoding by more than half without degrading the performance and increasing an amount of computation. The LDPC decoding method includes the steps of: receiving a prior probability information (channel values) based on information on channel values associated with distance between symbol signals in constellation related to the received noise and LDPC encoded data, and initializing bit nodes; dividing check nodes into partial groups before updating check node information based on the prior probability information, and performing a decoding by applying a sequential decoding algorithm; determining whether a parity check equations are satisfied; and outputting decoded messages obtained when satisfying the parity check equation or after terminating an iterative processor by a termination algorithm.
摘要:
Provided are an LDPC decoding apparatus and method using a sequential decoding algorithm having a partial group, capable of reducing the number of an iterative decoding by more than half without degrading the performance and increasing an amount of computation. The LDPC decoding method includes the steps of: receiving a prior probability information (channel values) based on information on channel values associated with distance between symbol signals in constellation related to the received noise and LDPC encoded data, and initializing bit nodes; dividing check nodes into partial groups before updating check node information based on the prior probability information, and performing a decoding by applying a sequential decoding algorithm; determining whether a parity check equations are satisfied; and outputting decoded messages obtained when satisfying the parity check equation or after terminating an iterative processor by a termination algorithm.
摘要:
A structure and a method for depuncturing an input bit stream being input to a Viterbi decoder when the Viterbi decoder is designed by using a Radix-4 branch metric calculator in a method for designing the Viterbi decoder that decodes a punctured code at a high-speed, are disclosed. A depuncture structure for Radix-4 branch metric calculation in a high-speed Viterbi decoder includes four FIFOs, four multiplexers, and one Radix-4 branch metric calculator. Two input bit streams of I and Q are connected to two upper FIFOs and two lower FIFOs. An output terminal of FIFO is connected to upper and lower multiplexers of the next stage. One output terminal of each multiplexer is connected to Radix-4 branch metric calculator. As a result, Radix-4 branch metric calculation can be achieved by using the same clock as a clock speed of the input I and Q bit streams. This structure and this method can be applied to a depuncturing process for Radix-4 branch metric calculation of all punctured codes derived from ½ code.
摘要:
Provided is a digital satellite broadcasting set-top box and a home network control system employing the same. The set-top box includes: a satellite signal receiving unit for receiving a satellite signal including a home network control signal for controlling the household appliances through a satellite broadcasting network from a remote terminal; and a control unit for extracting a household appliances control signal included in the satellite signal transmitted from the satellite signal receiving unit and commanding a power line converter to transmit the household appliances control signal to a corresponding household appliance, wherein the power line converter converts the household appliances control signal transmitted from the digital satellite broadcasting set-top box into a power line communication signal and transmits the power line communication signal on the home network through a power line.
摘要:
An apparatus allocates a channel used for inter-vehicle communications according to a traveling direction. The apparatus includes a traveling direction determiner for determining whether or not a traveling direction of a vehicle is changed; and a channel allocator for allocating the vehicle a previously allocated channel or a new channel based on a determined result of the traveling direction determiner. Further, a method allocates a channel used for inter-vehicle communications according to a traveling direction. The method includes the steps of determining whether or not a traveling direction of a vehicle is changed; and allocating the vehicle a previously allocated channel or a new channel based on a determined result in the above step.
摘要:
The present invention relates to a pre-processing apparatus using nonuniform quantization of a channel reliability value and a low density parity check (LDPC) decoding system. The pre-processing apparatus can present degradation in performance and be embodied simply by performing decoding pre-process by estimating a discrete channel reliability value (Lc*) through nonuniform quantization of a channel reliability value based on a relations between a bit error rate (BER) estimated through a simulation performed in advance and a standard deviation (σ) of channel noise within a predetermined range of noise estimation error and p, and bit-shifting a receiving signal as much as a discrete channel reliability value. The pre-processing apparatus includes: a channel reliability measuring unit, a nonuniform quantizing unit, a sign bit adding unit, a bit shifting unit.
摘要翻译:本发明涉及使用信道可靠性值和低密度奇偶校验(LDPC)解码系统的非均匀量化的预处理装置。 预处理装置可以呈现性能下降,并且通过基于信道可靠性值的非均匀量化来估计离散信道可靠性值(L> c * *)来执行解码预处理 通过预先执行的模拟估计的误码率(BER)与噪声估计误差和p的预定范围内的信道噪声的标准偏差(sigma)之间的关系,以及将接收信号与离散信道 可靠性值。 预处理装置包括:信道可靠性测量单元,不均匀量化单元,符号位加法单元,位移单元。