Quadrature demodulator for compensating for gain and phase imbalances between in-phase and quadrature-phase components
    1.
    发明授权
    Quadrature demodulator for compensating for gain and phase imbalances between in-phase and quadrature-phase components 失效
    用于补偿同相和正交相分量之间的增益和相位不平衡的正交解调器

    公开(公告)号:US07010059B2

    公开(公告)日:2006-03-07

    申请号:US10406094

    申请日:2003-04-02

    IPC分类号: H04L27/22

    摘要: Disclosed is a quadrature demodulator for high-speed wireless communication, which comprises: an A/D converter for converting received signals into digital signals; a signal recovery unit for recovering carriers and symbol timing from the signals converted by the A/D converter; a decision unit for detecting recovered signals output by the signal recovery unit, and performing a decision process on them; an I/Q gain imbalance detector for detecting gain imbalances of the I and Q-phase components from the recovered signals, and outputting an I/Q gain compensation value for compensating for the gain imbalances; and an I/Q gain compensator, provided between the A/D converter and the signal recovery unit, for reflecting the I/Q gain compensation value output by the I/Q gain imbalance detector to the received signals.

    摘要翻译: 公开了一种用于高速无线通信的正交解调器,其包括:A / D转换器,用于将接收到的信号转换成数字信号; 信号恢复单元,用于从由A / D转换器转换的信号中恢复载波和符号定时; 判定单元,用于检测由信号恢复单元输出的恢复信号,并对其进行决定处理; I / Q增益不平衡检测器,用于检测来自恢复信号的I相和Q相分量的增益不平衡,并输出用于补偿增益不平衡的I / Q增益补偿值; 以及设置在A / D转换器和信号恢复单元之间的用于将由I / Q增益不平衡检测器输出的I / Q增益补偿值反映到接收信号的I / Q增益补偿器。

    Apparatus for compensating phase of receiver and method thereof
    2.
    发明授权
    Apparatus for compensating phase of receiver and method thereof 失效
    用于补偿接收机相位的装置及其方法

    公开(公告)号:US07203251B2

    公开(公告)日:2007-04-10

    申请号:US10960415

    申请日:2004-10-06

    IPC分类号: H04L27/00 H00B7/212

    摘要: The present invention provides an apparatus for compensating a phase difference of a receiver, the apparatus including: an accumulating unit for accumulating a radio frequency (RF) input signal and generating an accumulated RF signal in order to minimize an effect of a background noise of the RF input signal; a early-local oscillating unit for generating a phase-early local oscillated signal based on a local oscillated signal of the receiver; a late-local oscillating unit for generating a phase-late local oscillated signal based on a local oscillated signal of the receiver; a phase early-late compensating unit for compensating a phase early-late based on the accumulated RF input signal and the phase-early and phase-late local oscillated signals; a look-up table data mapping unit for controlling a phase of the local oscillated signal with respect to a phase difference; and a feedback transmitting unit for transmitting a phase compensating data to the local oscillator.

    摘要翻译: 本发明提供了一种用于补偿接收机的相位差的装置,该装置包括:累加单元,用于累积射频(RF)输入信号并产生累积的RF信号,以便最小化背景噪声的影响 RF输入信号; 早期本地振荡单元,用于基于接收机的本地振荡信号产生相位早期本地振荡信号; 一个后局部振荡单元,用于基于接收器的本地振荡信号产生相位较晚的本地振荡信号; 一个相位早期补偿单元,用于基于累积的RF输入信号和相位早和相位晚的本地振荡信号来补偿相位的早期阶段; 查找表数据映射单元,用于控制相对于相位差的本地振荡信号的相位; 以及用于将相位补偿数据发送到本地振荡器的反馈发送单元。

    Apparatus for compensating phase of receiver and method thereof
    3.
    发明申请
    Apparatus for compensating phase of receiver and method thereof 失效
    用于补偿接收机相位的装置及其方法

    公开(公告)号:US20050141654A1

    公开(公告)日:2005-06-30

    申请号:US10960415

    申请日:2004-10-06

    IPC分类号: H04B1/28 H04L27/00 H04L27/06

    摘要: The present invention provides an apparatus for compensating a phase difference of a receiver, the apparatus including: an accumulating unit for accumulating a radio frequency (RF) input signal and generating an accumulated RF signal in order to minimize an effect of a background noise of the RF input signal; a early-local oscillating unit for generating a phase-early local oscillated signal based on a local oscillated signal of the receiver; a late-local oscillating unit for generating a phase-late local oscillated signal based on a local oscillated signal of the receiver; a phase early-late compensating unit for compensating a phase early-late based on the accumulated RF input signal and the phase-early and phase-late local oscillated signals; a look-up table data mapping unit for controlling a phase of the local oscillated signal with respect to a phase difference; and a feedback transmitting unit for transmitting a phase compensating data to the local oscillator.

    摘要翻译: 本发明提供了一种用于补偿接收机的相位差的装置,该装置包括:累加单元,用于累积射频(RF)输入信号并产生累积的RF信号,以便最小化背景噪声的影响 RF输入信号; 早期本地振荡单元,用于基于接收机的本地振荡信号产生相位早期本地振荡信号; 一个后局部振荡单元,用于基于接收器的本地振荡信号产生相位较晚的本地振荡信号; 一个相位早期补偿单元,用于基于累积的RF输入信号和相位早和相位晚的本地振荡信号来补偿相位的早期阶段; 查找表数据映射单元,用于控制相对于相位差的本地振荡信号的相位; 以及用于将相位补偿数据发送到本地振荡器的反馈发送单元。

    Method for detecting and correcting amplitude and phase imbalances between I and Q components in quadrature demodulator
    4.
    发明授权
    Method for detecting and correcting amplitude and phase imbalances between I and Q components in quadrature demodulator 失效
    用于检测和校正正交解调器中I和Q分量之间的幅度和相位不平衡的方法

    公开(公告)号:US06925132B2

    公开(公告)日:2005-08-02

    申请号:US10136307

    申请日:2002-05-02

    摘要: Disclosed is a method for detecting and correcting amplitude and phase imbalances between in-phase (I) and quadrature-phase (Q) components in a high-speed wireless communication quadrature demodulator, which comprises: a) comparing an input signal with a signal determined by a quadrant to which the input signal belongs, and detecting imbalances between I and Q components with respect to the input signal; and b) using the imbalances detected in a) to correct the input signal. The present invention prevents distorting of the demodulator's performance caused by the imbalances to between I and Q components and increases application to high-speed wireless communication.

    摘要翻译: 公开了一种用于检测和校正高速无线通信正交解调器中的同相(I)和正交相位(Q)分量之间的幅度和相位不平衡的方法,包括:a)将输入信号与确定的信号进行比较 通过输入信号所属的象限,并且相对于输入信号检测I和Q分量之间的不平衡; 和b)使用a)中检测到的不平衡来校正输入信号。 本发明可以防止由I和Q组件之间的不平衡引起的解调器的性能失真,并增加了对高速无线通信的应用。

    LDPC decoding apparatus and method with low computational complexity algorithm

    公开(公告)号:US20060136799A1

    公开(公告)日:2006-06-22

    申请号:US11265451

    申请日:2005-11-02

    IPC分类号: H03M13/00

    CPC分类号: H03M13/11

    摘要: Provided are an LDPC decoding apparatus and method using a sequential decoding algorithm having a partial group, capable of reducing the number of an iterative decoding by more than half without degrading the performance and increasing an amount of computation. The LDPC decoding method includes the steps of: receiving a prior probability information (channel values) based on information on channel values associated with distance between symbol signals in constellation related to the received noise and LDPC encoded data, and initializing bit nodes; dividing check nodes into partial groups before updating check node information based on the prior probability information, and performing a decoding by applying a sequential decoding algorithm; determining whether a parity check equations are satisfied; and outputting decoded messages obtained when satisfying the parity check equation or after terminating an iterative processor by a termination algorithm.

    LDPC decoding apparatus and method with low computational complexity algorithm
    6.
    发明授权
    LDPC decoding apparatus and method with low computational complexity algorithm 有权
    具有低计算复杂度算法的LDPC解码装置和方法

    公开(公告)号:US07539920B2

    公开(公告)日:2009-05-26

    申请号:US11265451

    申请日:2005-11-02

    IPC分类号: H03M13/00

    CPC分类号: H03M13/11

    摘要: Provided are an LDPC decoding apparatus and method using a sequential decoding algorithm having a partial group, capable of reducing the number of an iterative decoding by more than half without degrading the performance and increasing an amount of computation. The LDPC decoding method includes the steps of: receiving a prior probability information (channel values) based on information on channel values associated with distance between symbol signals in constellation related to the received noise and LDPC encoded data, and initializing bit nodes; dividing check nodes into partial groups before updating check node information based on the prior probability information, and performing a decoding by applying a sequential decoding algorithm; determining whether a parity check equations are satisfied; and outputting decoded messages obtained when satisfying the parity check equation or after terminating an iterative processor by a termination algorithm.

    摘要翻译: 提供了一种使用具有部分组的顺序解码算法的LDPC解码装置和方法,其能够将迭代解码的数量减少一半以上,而不降低性能并增加计算量。 LDPC解码方法包括以下步骤:基于与接收到的噪声相关的星座中的符号信号与LDPC编码数据之间的距离相关的信道值的信息,以及初始化比特节点,接收先验概率信息(信道值) 在根据先验概率信息更新校验节点信息之前,将校验节点划分为部分组,并通过应用顺序解码算法执行解码; 确定是否满足奇偶校验方程; 并输出在满足奇偶校验方程时获得的解码消息,或者通过终止算法终止迭代处理器。

    Structure and method for depuncturing punctured codes for radix-4 branch metric calculation in high-speed viterbi decoder
    7.
    发明授权
    Structure and method for depuncturing punctured codes for radix-4 branch metric calculation in high-speed viterbi decoder 有权
    用于在高速维特比解码器中进行基数4分支度量计算的去穿孔穿孔码的结构和方法

    公开(公告)号:US06732326B2

    公开(公告)日:2004-05-04

    申请号:US09846477

    申请日:2001-04-30

    IPC分类号: H03M1341

    摘要: A structure and a method for depuncturing an input bit stream being input to a Viterbi decoder when the Viterbi decoder is designed by using a Radix-4 branch metric calculator in a method for designing the Viterbi decoder that decodes a punctured code at a high-speed, are disclosed. A depuncture structure for Radix-4 branch metric calculation in a high-speed Viterbi decoder includes four FIFOs, four multiplexers, and one Radix-4 branch metric calculator. Two input bit streams of I and Q are connected to two upper FIFOs and two lower FIFOs. An output terminal of FIFO is connected to upper and lower multiplexers of the next stage. One output terminal of each multiplexer is connected to Radix-4 branch metric calculator. As a result, Radix-4 branch metric calculation can be achieved by using the same clock as a clock speed of the input I and Q bit streams. This structure and this method can be applied to a depuncturing process for Radix-4 branch metric calculation of all punctured codes derived from ½ code.

    摘要翻译: 在维特比解码器被设计成通过在设计维特比解码器的方法中设计的维特比解码器的结构和方法被输入到维特比解码器,该维特比解码器以高速解码穿孔码 ,被披露。 在高速维特比解码器中用于基数4分支度量计算的解穿孔结构包括四个FIFO,四个多路复用器和一个基数-4分支度量计算器。 I和Q的两个输入比特流连接到两个较高的FIFO和两个较低的FIFO。 FIFO的输出端子连接到下一级的上下复用器。 每个多路复用器的一个输出端连接到基数-4分支度量计算器。 因此,可以通过使用与输入I和Q位流的时钟速度相同的时钟来实现基数-4分支度量计算。 该结构和该方法可以应用于从½码导出的所有穿孔码的基数-4分支度量计算的解穿孔过程。

    Digital satellite broadcasting set-top box, and home network control system employing the same
    8.
    发明申请
    Digital satellite broadcasting set-top box, and home network control system employing the same 审中-公开
    数字卫星广播机顶盒和家庭网络控制系统采用相同

    公开(公告)号:US20070130598A1

    公开(公告)日:2007-06-07

    申请号:US11607637

    申请日:2006-11-30

    摘要: Provided is a digital satellite broadcasting set-top box and a home network control system employing the same. The set-top box includes: a satellite signal receiving unit for receiving a satellite signal including a home network control signal for controlling the household appliances through a satellite broadcasting network from a remote terminal; and a control unit for extracting a household appliances control signal included in the satellite signal transmitted from the satellite signal receiving unit and commanding a power line converter to transmit the household appliances control signal to a corresponding household appliance, wherein the power line converter converts the household appliances control signal transmitted from the digital satellite broadcasting set-top box into a power line communication signal and transmits the power line communication signal on the home network through a power line.

    摘要翻译: 提供了一种数字卫星广播机顶盒和采用其的家庭网络控制系统。 机顶盒包括:卫星信号接收单元,用于通过卫星广播网络从远程终端接收包括用于控制家用电器的家庭网络控制信号的卫星信号; 以及控制单元,用于提取从卫星信号接收单元发送的卫星信号中包含的家用电器控制信号,并指示电力线转换器将家用电器控制信号发送到相应的家用电器,其中电力线转换器将家庭 家用电器控制信号从数字卫星广播机顶盒发送到电力线通信信号,并通过电力线在家庭网络上发送电力线通信信号。

    Apparatus and method for channel allocation according to traveling direction in inter-vehicle communications
    9.
    发明授权
    Apparatus and method for channel allocation according to traveling direction in inter-vehicle communications 有权
    根据车辆间通信中的行进方向进行信道分配的装置和方法

    公开(公告)号:US07750823B2

    公开(公告)日:2010-07-06

    申请号:US11776161

    申请日:2007-07-11

    IPC分类号: G08G1/08

    CPC分类号: G08G1/161 G08G1/056

    摘要: An apparatus allocates a channel used for inter-vehicle communications according to a traveling direction. The apparatus includes a traveling direction determiner for determining whether or not a traveling direction of a vehicle is changed; and a channel allocator for allocating the vehicle a previously allocated channel or a new channel based on a determined result of the traveling direction determiner. Further, a method allocates a channel used for inter-vehicle communications according to a traveling direction. The method includes the steps of determining whether or not a traveling direction of a vehicle is changed; and allocating the vehicle a previously allocated channel or a new channel based on a determined result in the above step.

    摘要翻译: 一种装置根据行驶方向分配用于车辆间通信的信道。 该装置包括用于确定车辆的行进方向是否改变的行进方向确定器; 以及信道分配器,用于基于行进方向确定器的确定结果来分配车辆先前分配的信道或新信道。 此外,方法根据行驶方向分配用于车辆间通信的信道。 该方法包括以下步骤:确定车辆行驶方向是否改变; 以及在上述步骤中基于所确定的结果来分配车辆先前分配的信道或新信道。

    Pre-processing apparatus using nonuniform quantization of channel reliability value and LDPC decoding system using the same
    10.
    发明申请
    Pre-processing apparatus using nonuniform quantization of channel reliability value and LDPC decoding system using the same 失效
    使用信道可靠性值的非均匀量化的预处理装置和使用其的LDPC解码系统

    公开(公告)号:US20050144543A1

    公开(公告)日:2005-06-30

    申请号:US10888167

    申请日:2004-07-09

    IPC分类号: G06F11/00

    摘要: The present invention relates to a pre-processing apparatus using nonuniform quantization of a channel reliability value and a low density parity check (LDPC) decoding system. The pre-processing apparatus can present degradation in performance and be embodied simply by performing decoding pre-process by estimating a discrete channel reliability value (Lc*) through nonuniform quantization of a channel reliability value based on a relations between a bit error rate (BER) estimated through a simulation performed in advance and a standard deviation (σ) of channel noise within a predetermined range of noise estimation error and p, and bit-shifting a receiving signal as much as a discrete channel reliability value. The pre-processing apparatus includes: a channel reliability measuring unit, a nonuniform quantizing unit, a sign bit adding unit, a bit shifting unit.

    摘要翻译: 本发明涉及使用信道可靠性值和低密度奇偶校验(LDPC)解码系统的非均匀量化的预处理装置。 预处理装置可以呈现性能下降,并且通过基于信道可靠性值的非均匀量化来估计离散信道可靠性值(L> c * *)来执行解码预处理 通过预先执行的模拟估计的误码率(BER)与噪声估计误差和p的预定范围内的信道噪声的标准偏差(sigma)之间的关系,以及将接收信号与离散信道 可靠性值。 预处理装置包括:信道可靠性测量单元,不均匀量化单元,符号位加法单元,位移单元。