公开(公告)号：US5600802A

公开(公告)日：1997-02-04

申请号：US212457

申请日：1994-03-14

申请人： Farid A. Yazdy ,  Michael J. Dhuey

发明人： Farid A. Yazdy ,  Michael J. Dhuey

IPC分类号： G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4063

摘要： Circuit arrangements and methods are disclosed for upgrading an 040-based personal computer system using an optional, peripheral add-in card. In one embodiment, the present invention comprises a PowerPC-based microprocessor, such as the MPC601, having one megabyte of on-board direct mapped level 2 external cache memory arranged as tag and data blocks. The PowerPC-based board is inserted into a processor-direct data path sharing the data and address bus with the 040 microprocessor. System random access memory (RAM), I/O, and other functional blocks are present on the main board comprising the 040-based computer. The MPC601 is coupled via address and data buses to the tag cache, a bus translation unit (BTU), a read only memory (ROM) storing the operating system code for the PowerPC microprocessor, the data cache, a dual frequency clock buffer, and other interface components such as a processor-direct data path including address and data latches. When the computer is turned on, the BTU coupled to the data bus sequentially clears all valid bits in the tag cache, whereafter the cache and memory map are enabled. The 040 processor on the main board is disabled after power-up by using the 040 JTAG test port after inactivating the power-on fast reset. By shifting in appropriate RESET, TCK, and TMS patterns, the 040 will be placed in a nonfunctional, high impedance state. However, DRAM present on the motherboard may be accessed by the 601 after a cache miss. DRAM is accessed via a 601-040 transaction translation operation within the BTU, wherein coded tables map the MPC601 transaction into the appropriate 040 transaction.

摘要翻译： 公开了用于使用可选的外围附加卡升级基于040的个人计算机系统的电路布置和方法。 在一个实施例中，本发明包括基于PowerPC的微处理器，诸如MPC601，其具有布置为标签和数据块的一兆字节的车载直接映射级2外部高速缓冲存储器。 基于PowerPC的电路板插入与040微处理器共享数据和地址总线的处理器直接数据通路。 系统随机存取存储器（RAM），I / O和其他功能块存在于包含基于040的计算机的主板上。 MPC601通过地址和数据总线耦合到标签缓存，总线转换单元（BTU），存储用于PowerPC微处理器的操作系统代码的只读存储器（ROM），数据高速缓存，双频时钟缓冲器和 其他接口组件，例如包括地址和数据锁存器的处理器直接数据路径。 当计算机打开时，耦合到数据总线的BTU顺序地清除标签高速缓存中的所有有效位，之后启用高速缓存和存储器映射。 上电后，主板上的040处理器在禁用上电快速复位后使用040 JTAG测试端口禁用。 通过在适当的RESET，TCK和TMS模式下移位，040将处于非功能，高阻抗状态。 然而，存在于主板上的DRAM可能在高速缓存未命中之后由601访问。 通过BTU内的601-040事务翻译操作访问DRAM，其中编码表将MPC601事务映射到适当的040事务。

公开(公告)号：US5515514A

公开(公告)日：1996-05-07

申请号：US535761

申请日：1995-09-28

申请人： Michael J. Dhuey ,  Farid A. Yazdy

发明人： Michael J. Dhuey ,  Farid A. Yazdy

IPC分类号： G06F12/08 ,  G06F13/40 ,  G06F15/76

CPC分类号： G06F12/0866 ,  G06F13/4068

摘要： Circuit arrangements and methods are disclosed for upgrading an 040-based personal computer system using an optional, peripheral add-in card. In one embodiment, the present invention comprises a PowerPC-based microprocessor, such as the MPC601, having one megabyte of on-board direct mapped level 2 external cache memory arranged as tag and data blocks. The PowerPC-based board is inserted into a processor-direct data path sharing the data and address bus with the 040 microprocessor. System random access memory (RAM), I/O, and other functional blocks are present on the main board comprising the 040-based computer. The MPC601 is coupled via address and data buses to the tag cache, a bus translation unit (BTU), a read only memory (ROM) storing the operating system code for the PowerPC microprocessor, the data cache, a dual frequency clock buffer, and other interface components such as a processor-direct data path including address and data latches. When the computer is turned on, the BTU coupled to the data bus sequentially clears all valid bits in the tag cache, whereafter the cache and memory map are enabled. The 040 processor on the main board is disabled after power-up by using the 040 JTAG test port after inactivating the power-on fast reset. By shifting in appropriate RESET, TCK, and TMS patterns, the 040 will be placed in a nonfunctional, high impedance state. However, DRAM present on the motherboard may be accessed by the 601 after a cache miss. DRAM is accessed via a 601-040 transaction translation operation within the BTU, wherein coded tables map the MPC601 transaction into the appropriate 040 transaction.

摘要翻译： 公开了用于使用可选的外围附加卡升级基于040的个人计算机系统的电路布置和方法。 在一个实施例中，本发明包括基于PowerPC的微处理器，诸如MPC601，其具有布置为标签和数据块的一兆字节的车载直接映射级2外部高速缓冲存储器。 基于PowerPC的电路板插入与040微处理器共享数据和地址总线的处理器直接数据通路。 系统随机存取存储器（RAM），I / O和其他功能块存在于包含基于040的计算机的主板上。 MPC601通过地址和数据总线耦合到标签缓存，总线转换单元（BTU），存储用于PowerPC微处理器的操作系统代码的只读存储器（ROM），数据高速缓存，双频时钟缓冲器和 其他接口组件，例如包括地址和数据锁存器的处理器直接数据路径。 当计算机打开时，耦合到数据总线的BTU顺序地清除标签高速缓存中的所有有效位，之后启用高速缓存和存储器映射。 上电后，主板上的040处理器在禁用上电快速复位后使用040 JTAG测试端口禁用。 通过在适当的RESET，TCK和TMS模式下移位，040将处于非功能，高阻抗状态。 然而，存在于主板上的DRAM可能在高速缓存未命中之后由601访问。 通过BTU内的601-040事务翻译操作访问DRAM，其中编码表将MPC601事务映射到适当的040事务。

公开(公告)号：US5603007A

公开(公告)日：1997-02-11

申请号：US212081

申请日：1994-03-14

申请人： Farid A. Yazdy ,  Michael J. Dhuey

发明人： Farid A. Yazdy ,  Michael J. Dhuey

IPC分类号： G06F12/08

CPC分类号： G06F12/0879

摘要： Circuit arrangements and methods are disclosed for upgrading an 040-based personal computer system using an optional, peripheral add-in card. In one embodiment, the present invention comprises a PowerPC-based microprocessor, such as the MPC601, having one megabyte of on-board direct mapped level 2 external cache memory arranged as tag and data blocks. The PowerPC-based board is inserted into a processor-direct data path sharing the data and address bus with the 040 microprocessor. System random access memory (RAM), I/O, and other functional blocks are present on the main board comprising the 040-based computer. The MPC601 is coupled via address and data buses to the tag cache, a bus translation unit (BTU), a read only memory (ROM) storing the operating system code for the PowerPC microprocessor, the data cache, a dual frequency clock buffer, and other interface components such as a processor-direct data path including address and data latches. When the computer is turned on, the BTU coupled to the data bus sequentially clears all valid bits in the tag cache, whereafter the cache and memory map are enabled. The 040 processor on the main board is disabled after power-up by using the 040 JTAG test port after inactivating the power-on fast reset. By shifting in appropriate RESET, TCK, and TMS patterns, the 040 will be placed in a nonfunctional, high impedance state. However, DRAM present on the motherboard may be accessed by the 601 after a cache miss. DRAM is accessed via a 601-040 transaction translation operation within the BTU, wherein coded tables map the MPC601 transaction into the appropriate 040 transaction.

摘要翻译： 公开了用于使用可选的外围附加卡升级基于040的个人计算机系统的电路布置和方法。 在一个实施例中，本发明包括基于PowerPC的微处理器，诸如MPC601，其具有布置为标签和数据块的一兆字节的车载直接映射级2外部高速缓冲存储器。 基于PowerPC的电路板插入与040微处理器共享数据和地址总线的处理器直接数据通路。 系统随机存取存储器（RAM），I / O和其他功能块存在于包含基于040的计算机的主板上。 MPC601通过地址和数据总线耦合到标签缓存，总线转换单元（BTU），存储用于PowerPC微处理器的操作系统代码的只读存储器（ROM），数据高速缓存，双频时钟缓冲器和 其他接口组件，例如包括地址和数据锁存器的处理器直接数据路径。 当计算机打开时，耦合到数据总线的BTU顺序地清除标签高速缓存中的所有有效位，之后启用高速缓存和存储器映射。 上电后，主板上的040处理器在禁用上电快速复位后使用040 JTAG测试端口禁用。 通过在适当的RESET，TCK和TMS模式下移位，040将处于非功能，高阻抗状态。 然而，存在于主板上的DRAM可能在高速缓存未命中之后由601访问。 通过BTU内的601-040事务翻译操作访问DRAM，其中编码表将MPC601事务映射到适当的040事务。

公开(公告)号：US5500827A

公开(公告)日：1996-03-19

申请号：US514367

申请日：1995-08-11

申请人： Farid A. Yazdy ,  Michael J. Dhuey

发明人： Farid A. Yazdy ,  Michael J. Dhuey

IPC分类号： G06F13/16 ,  G11C11/406 ,  G11C11/24 ,  G11C11/40

CPC分类号： G11C11/406 ,  G06F13/1636

摘要： The present invention facilitates the Dynamic Random Access Memory (DRAM) refresh function in a less obtrusive manner than in the prior art. The present invention facilitates the refresh function during idle time when the DRAM is not busy handling read or write transactions. If insufficient idle time exists then the present invention will force a refresh operation thus ensuring that all memory cells are maintained in a properly charged state.

摘要翻译： 本发明以比现有技术更少的突出方式促进了动态随机存取存储器（DRAM）刷新功能。 本发明有助于在DRAM不忙于处理读或写事务的空闲时间期间的刷新功能。 如果存在空闲时间不足，则本发明将强制进行刷新操作，从而确保所有存储器单元保持在适当的充电状态。

公开(公告)号：US5237573A

公开(公告)日：1993-08-17

申请号：US860950

申请日：1992-03-31

申请人： Michael J. Dhuey ,  Farid A. Yazdy

发明人： Michael J. Dhuey ,  Farid A. Yazdy

IPC分类号： G11C5/06 ,  G11C8/00 ,  H03K17/00

CPC分类号： H03K17/005 ,  G11C5/066 ,  G11C8/00

摘要： The present invention selectively switches between two or more input signals while avoiding invalid output conditions, large power draws, and the resulting electromagnetic interference caused thereby. The present invention can be used to select between Dynamic Random Access Memory device column addresses and Dynamic Random Access Memory device row addresses.

摘要翻译： 本发明有选择地在两个或多个输入信号之间切换，同时避免无效的输出条件，大功率消耗以及由此引起的所产生的电磁干扰。 本发明可用于在动态随机存取存储器设备列地址和动态随机存取存储器器件行地址之间进行选择。

公开(公告)号：US07541698B2

公开(公告)日：2009-06-02

申请号：US11824639

申请日：2007-07-02

申请人： Michael J. Dhuey

发明人： Michael J. Dhuey

IPC分类号： H01H35/00

CPC分类号： H05K7/20209 ,  F04D27/004 ,  G06F1/206 ,  Y10T307/858

摘要： A novel circuit for driving a fan includes an output terminal for supplying the fan with drive power, a pulse width modulation driver, and a limiter. A first power terminal of the fan is held at a first voltage (e.g., 0V), and a second power terminal of the fan is coupled to the output terminal of the driver circuit. The PWM driver provides a series of fan drive pulses on the output terminal, and the limiter prevents the voltage on the output terminal from falling below a predetermined voltage. The predetermined voltage is greater than the first voltage at which the fan's first power terminal is held, and is sufficient to keep the fan in motion even when the duty cycle of the PWM signal is 0%. In a particular embodiment the limiter includes a voltage clamp. In a more particular embodiment, the voltage clamp is a diode. In another particular embodiment the limiter includes a switch for combining a PWM signal with a DC voltage at an output.

摘要翻译： 用于驱动风扇的新颖电路包括用于向风扇供应驱动电力的输出端子，脉宽调制驱动器和限幅器。 风扇的第一电源端子保持在第一电压（例如0V），并且风扇的第二电源端子耦合到驱动器电路的输出端子。 PWM驱动器在输出端子上提供一系列风扇驱动脉冲，并且限幅器防止输出端子上的电压下降到预定电压以下。 预定电压大于风扇第一电源端子保持的第一电压，并且即使当PWM信号的占空比为0％时也足以使风扇保持运动。 在特定实施例中，限幅器包括电压钳。 在更具体的实施例中，电压钳是二极管。 在另一特定实施例中，限幅器包括用于在输出处将PWM信号与DC电压组合的开关。

公开(公告)号：US06924568B2

公开(公告)日：2005-08-02

申请号：US10214414

申请日：2002-08-06

申请人： Michael J. Dhuey

发明人： Michael J. Dhuey

IPC分类号： G06F1/20 ,  H05K7/20 ,  H01H35/00

CPC分类号： H05K7/20209 ,  F04D27/004 ,  G06F1/206 ,  Y10T307/858

摘要： A novel a circuit for driving a fan includes an output terminal for supplying the fan with drive power, a pulse width modulation driver, and a limiter. A first power terminal of the fan is held at a first voltage (e.g., 0V), and a second power terminal of the fan is coupled to the output terminal of the driver circuit. The PWM driver provides a series of fan drive pulses on the output terminal, and the limiter prevents the voltage on the output terminal from falling below a predetermined voltage. The predetermined voltage is greater than the first voltage at which the fan's first power terminal is held, and is sufficient to keep the fan in motion even when the duty cycle of the PWM signal is 0%. In a particular embodiment the limiter includes a voltage clamp. In a more particular embodiment, the voltage clamp is a diode. In another particular embodiment, the limiter includes a switch for combining a PWM signal with a DC voltage at an output.

摘要翻译： 用于驱动风扇的新型电路包括用于向风扇供应驱动电力的输出端子，脉宽调制驱动器和限幅器。 风扇的第一电源端子保持在第一电压（例如0V），并且风扇的第二电源端子耦合到驱动器电路的输出端子。 PWM驱动器在输出端子上提供一系列风扇驱动脉冲，并且限幅器防止输出端子上的电压下降到预定电压以下。 预定电压大于风扇第一电源端子保持的第一电压，并且即使当PWM信号的占空比为0％时也足以使风扇保持运动。 在特定实施例中，限幅器包括电压钳。 在更具体的实施例中，电压钳是二极管。 在另一特定实施例中，限幅器包括一个开关，用于将PWM信号与输出端的直流电压进行组合。

公开(公告)号：US08427523B2

公开(公告)日：2013-04-23

申请号：US12724092

申请日：2010-03-15

申请人： Randy K. Harrell ,  Michael J. Dhuey ,  Richard T. Wales ,  Philip E. Marechal ,  Philip R. Graham ,  Ashok T. Desai ,  Andrew D. Grunes ,  Tark Abed ,  Pete Lombrozo ,  Peter H. J. How

发明人： Randy K. Harrell ,  Michael J. Dhuey ,  Richard T. Wales ,  Philip E. Marechal ,  Philip R. Graham ,  Ashok T. Desai ,  Andrew D. Grunes ,  Tark Abed ,  Pete Lombrozo ,  Peter H. J. How

IPC分类号： H04N7/14

CPC分类号： H04N7/144 ,  H04N7/15

摘要： A system for enhancing eye gaze in a telepresence system includes a plurality of local cameras coupled to at least one local display. Each local camera is directed to at least one respective local user section and operable to generate an image of the respective local user section. The system also includes a plurality of remote displays. Each remote display is operable to reproduce the local video image of the local user section. Within the system the plurality of remote displays and the plurality of local cameras are aligned such that when a first local user within a local user section looks at a target at least one remote display is operable to reproduce the local video image of the first user section comprising the first local user such that the eye gaze of the reproduced image of the first local user is directed approximately at a corresponding target.

摘要翻译： 用于在远程呈现系统中增强眼睛注视的系统包括耦合到至少一个本地显示器的多个本地摄像机。 每个本地摄像机被引导到至少一个相应的本地用户部分并且可操作以生成相应的本地用户部分的图像。 该系统还包括多个远程显示器。 每个远程显示器可操作以再现本地用户部分的本地视频图像。 在系统内，多个远程显示器和多个本地摄像机对准，使得当本地用户部分内的第一本地用户查看目标时，至少一个远程显示器可操作以再现第一用户部分的本地视频图像 包括第一本地用户，使得第一本地用户的再现图像的眼睛注视大致对应于相应的目标。

公开(公告)号：US20100171808A1

公开(公告)日：2010-07-08

申请号：US12724092

申请日：2010-03-15

申请人： Randy K. Harrell ,  Michael J. Dhuey ,  Richard T. Wales ,  Philip E. Marechal ,  Philip R. Graham ,  Ashok T. Desai ,  Andrew D. Grunes ,  Tark Abed ,  Pete Lombrozo ,  Peter H.J. How

发明人： Randy K. Harrell ,  Michael J. Dhuey ,  Richard T. Wales ,  Philip E. Marechal ,  Philip R. Graham ,  Ashok T. Desai ,  Andrew D. Grunes ,  Tark Abed ,  Pete Lombrozo ,  Peter H.J. How

IPC分类号： H04N7/14

CPC分类号： H04N7/144 ,  H04N7/15

摘要： A system for enhancing eye gaze in a telepresence system includes a plurality of local cameras coupled to at least one local display. Each local camera is directed to at least one respective local user section and operable to generate an image of the respective local user section. The system also includes a plurality of remote displays. Each remote display is operable to reproduce the local video image of the local user section. Within the system the plurality of remote displays and the plurality of local cameras are aligned such that when a first local user within a local user section looks at a target at least one remote display is operable to reproduce the local video image of the first user section comprising the first local user such that the eye gaze of the reproduced image of the first local user is directed approximately at a corresponding target.

摘要翻译： 用于在远程呈现系统中增强眼睛注视的系统包括耦合到至少一个本地显示器的多个本地摄像机。 每个本地摄像机被引导到至少一个相应的本地用户部分并且可操作以生成相应的本地用户部分的图像。 该系统还包括多个远程显示器。 每个远程显示器可操作以再现本地用户部分的本地视频图像。 在系统内，多个远程显示器和多个本地摄像机对准，使得当本地用户部分内的第一本地用户查看目标时，至少一个远程显示器可操作以再现第一用户部分的本地视频图像 包括第一本地用户，使得第一本地用户的再现图像的眼睛注视大致对应于相应的目标。

公开(公告)号：US07710450B2

公开(公告)日：2010-05-04

申请号：US11456339

申请日：2006-07-10

申请人： Michael J. Dhuey ,  Philip R. Graham ,  Richard T. Wales

发明人： Michael J. Dhuey ,  Philip R. Graham ,  Richard T. Wales

IPC分类号： H04N7/14 ,  H04N5/232

CPC分类号： H04N7/142 ,  G06F3/14 ,  G09G5/005 ,  G09G2340/0442 ,  G09G2354/00 ,  G09G2370/02 ,  G09G2370/10 ,  H04N5/23203 ,  H04N5/2353

摘要： A system and method are provided for capturing and transmitting frames in a video conference. The method comprises determining a frame rate and a shutter speed according to variable control data, capturing image data according to the determined shutter speed, and transmitting the captured image data through a communication interface to a remote video conference system. The variable control data specifies a relationship between the frame rate and the shutter speed.

摘要翻译： 提供了一种用于在视频会议中捕获和发送帧的系统和方法。 该方法包括根据可变控制数据确定帧率和快门速度，根据所确定的快门速度拍摄图像数据，以及通过通信接口将捕获的图像数据发送到远程视频会议系统。 可变控制数据指定帧速率和快门速度之间的关系。