公开(公告)号：US20180240883A1

公开(公告)日：2018-08-23

申请号：US15955989

申请日：2018-04-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： DANIEL CHANEMOUGAME ,  ANDRE LABONTE ,  RUILONG XIE ,  LARS LIEBMANN ,  NIGEL CAVE ,  GUILLAUME BOUCHE

IPC: H01L29/49 ,  H01L21/764 ,  H01L29/66

CPC classification number: H01L29/4991 ,  H01L21/0217 ,  H01L21/28141 ,  H01L21/30604 ,  H01L21/764 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823821 ,  H01L21/845 ,  H01L23/535 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10826 ,  H01L27/10844 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66689 ,  H01L29/66719 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L2924/13067

Abstract: Disclosed are integrated circuit (IC) structures and formation methods. In the methods, a gate with a sacrificial gate cap and a sacrificial gate sidewall spacer is formed on a channel region. The cap and sidewall spacer are removed, creating a cavity with a lower portion between the sidewalls of the gate and adjacent metal plugs and with an upper portion above the lower portion and the gate. A first dielectric layer is deposited, forming an air-gap in the lower portion and lining the upper portion. A second dielectric layer is deposited, filling the upper portion. During formation of a gate contact opening (optionally over an active region), the second dielectric layer is removed and the first dielectric layer is anisotropically etched, thereby exposing the gate and creating a dielectric spacer with a lower air-gap segment and an upper solid segment. Metal deposited into the opening forms the gate contact.

公开(公告)号：US20180204927A1

公开(公告)日：2018-07-19

申请号：US15408540

申请日：2017-01-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： DANIEL CHANEMOUGAME ,  ANDRE LABONTE ,  RUILONG XIE ,  LARS LIEBMANN ,  NIGEL CAVE ,  GUILLAUME BOUCHE

IPC: H01L29/49 ,  H01L23/535 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L29/4991 ,  H01L21/0217 ,  H01L21/28141 ,  H01L21/30604 ,  H01L21/764 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823821 ,  H01L21/845 ,  H01L23/535 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10826 ,  H01L27/10844 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66689 ,  H01L29/66719 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L2924/13067

Abstract: Disclosed are integrated circuit (IC) structures and formation methods. In the methods, a gate with a sacrificial gate cap and a sacrificial gate sidewall spacer is formed on a channel region. The cap and sidewall spacer are removed, creating a cavity with a lower portion between the sidewalls of the gate and adjacent metal plugs and with an upper portion above the lower portion and the gate. A first dielectric layer is deposited, forming an air-gap in the lower portion and lining the upper portion. A second dielectric layer is deposited, filling the upper portion. During formation of a gate contact opening (optionally over an active region), the second dielectric layer is removed and the first dielectric layer is anisotropically etched, thereby exposing the gate and creating a dielectric spacer with a lower air-gap segment and an upper solid segment. Metal deposited into the opening forms the gate contact.