公开(公告)号：US09299590B1

公开(公告)日：2016-03-29

申请号：US14743030

申请日：2015-06-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Richard S. Graf ,  Ezra D. B. Hall ,  Vibhor Jain ,  Jack R. Smith ,  Sebastian T. Ventrone

IPC: H01L21/66 ,  H01L21/48 ,  H01L21/78 ,  H01L21/768 ,  H01L21/56 ,  H01L23/38 ,  H01L23/367

CPC classification number: H01L23/38 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Various particular embodiments include a method of forming an integrated circuit (IC) device including: forming at least one thermoelectric cooling device over an upper surface of a handle wafer based upon a known location of an elevated temperature region in the IC device; forming a first oxide layer over the handle wafer covering the thermoelectric cooling device; forming a second oxide layer over a donor silicon wafer to form a donor wafer; bonding the donor wafer to the handle wafer at the first oxide layer and the second oxide layer, such that the second oxide layer contacts the first oxide layer on the handle wafer; and forming at least one semiconductor device over the donor silicon wafer side of the donor wafer, wherein the at least one thermoelectric cooling device is located proximate the at least one semiconductor device.

Abstract translation: 各种具体实施例包括形成集成电路（IC）装置的方法，包括：基于IC器件中的升高温度区域的已知位置，在处理晶片的上表面上形成至少一个热电冷却装置; 在覆盖所述热电冷却装置的所述处理晶片上形成第一氧化物层; 在供体硅晶片上形成第二氧化物层以形成施主晶片; 在第一氧化物层和第二氧化物层处将施主晶片接合到处理晶片，使得第二氧化物层接触处理晶片上的第一氧化物层; 以及在施主晶片的供体硅晶片侧上形成至少一个半导体器件，其中所述至少一个热电冷却器件位于所述至少一个半导体器件附近。

公开(公告)号：US20210033660A1

公开(公告)日：2021-02-04

申请号：US16527146

申请日：2019-07-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sebastian T. Ventrone ,  Richard S. Graf ,  Ezra D. B. Hall ,  Jack R. Smith

IPC: G01R31/28 ,  H04L9/32

Abstract: An integrated circuit (IC) includes functional logic therein that can be enabled by application of a predefined thermal cycle. The IC includes an enabling fuse operatively coupled to the functional logic, the functional logic being disabled unless enabled by activation of the enabling fuse. A set of thermal sensors are arranged in a physically distributed manner through at least a portion of the IC. A test control macro operatively couples to the set of thermal sensors and the enabling fuse for activating the enabling fuse to enable the functional logic in response to application of a thermal cycle that causes the set of thermal sensors to sequentially experience a thermal condition matching a thermal sequence enabling test. A related method and system for applying the predefined thermal cycle are also provided.

公开(公告)号：US20170255471A1

公开(公告)日：2017-09-07

申请号：US15062302

申请日：2016-03-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jack R. Smith ,  Sebastian T. Ventrone ,  Ezra D. B. Hall

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/08 ,  G06F3/06

CPC classification number: G06F9/3832 ,  G06F9/3808

Abstract: Various embodiments include processors for processing operations. In some cases, a processor includes: an instruction fetch component configured to fetch processing instructions; an instruction cache component connected with the instruction fetch component, configured to store the processing instructions; an execution component connected with the instruction cache component, configured to execute the processing instructions; a monitor component connected with the execution component, configured to receive execution results from the processing instructions; and a content addressable memory (CAM) component connected with the instruction fetch component and the monitor component, wherein the monitor component stores a portion of the execution results in the CAM for subsequent use in bypassing the execution component.

公开(公告)号：US10083891B1

公开(公告)日：2018-09-25

申请号：US15789108

申请日：2017-10-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Richard S. Graf ,  Sebastian T. Ventrone ,  Ezra D. B. Hall

IPC: H01L23/38 ,  H01L27/108 ,  H01L23/34 ,  H01L25/16 ,  H01L23/498 ,  H01L23/48 ,  H01L23/367 ,  H01L35/10

CPC classification number: H01L23/38 ,  H01L23/34 ,  H01L23/345 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/5384 ,  H01L23/5385 ,  H01L25/16 ,  H01L27/10897 ,  H01L35/10 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/15311

Abstract: An IC chip package includes: a base substrate; an interposer substrate including a plurality of wires therein, the interposer substrate operatively coupled to the base substrate; and a processor operatively positioned on the interposer substrate. A memory is operatively positioned on the interposer substrate and operatively coupled to the processor through the interposer substrate. The memory includes: a 3D DRAM stack, a thermoelectric heat pump coupled directly to an uppermost layer of the 3D DRAM stack, and a memory controller operatively coupled to the 3D DRAM stack to control operation of the 3D DRAM stack. A temperature controller operatively coupled to the thermoelectric heat pump controls a temperature of the 3D DRAM stack using the thermoelectric heat pump. A lid may thermally couple to an uppermost surface of the processor and an uppermost surface of the thermoelectric heat pump.