公开(公告)号：US09690898B2

公开(公告)日：2017-06-27

申请号：US14749909

申请日：2015-06-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ioana C. Graur ,  Ian P. Stobert ,  Dmitry A. Vengertsev

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G06F17/5068 ,  G06F17/5077

Abstract: Candidate layout patterns can be generated using a generative model trained based on known data, such as historical hot spot data, features extraction, and geometrical primitives. The generative model can be sampled to obtain candidate layouts that can be ranked and repaired using error optimization, design rule checking, optical proximity checking, and other methods to ensure that resulting candidates are manufacturable.

公开(公告)号：US20160378902A1

公开(公告)日：2016-12-29

申请号：US14749909

申请日：2015-06-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ioana C. Graur ,  Ian P. Stobert ,  Dmitry A. Vengertsev

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G06F17/5068 ,  G06F17/5077

Abstract: Candidate layout patterns can be generated using a generative model trained based on known data, such as historical hot spot data, features extraction, and geometrical primitives. The generative model can be sampled to obtain candidate layouts that can be ranked and repaired using error optimization, design rule checking, optical proximity checking, and other methods to ensure that resulting candidates are manufacturable.

Abstract translation: 可以使用基于已知数据（例如历史热点数据，特征提取和几何图元）训练的生成模型来生成候选布局模式。 可以对生成模型进行采样，以获得可以使用错误优化，设计规则检查，光学邻近检查和其他方法进行排名和修复的候选布局，以确保生成的候选者是可制造的。

公开(公告)号：US09311443B2

公开(公告)日：2016-04-12

申请号：US14306715

申请日：2014-06-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dureseti Chidambarrao ,  James A. Culp ,  Paul C. Parries ,  Ian P. Stobert

IPC: G06F17/50

CPC classification number: H01L27/0207 ,  G03F7/70433 ,  G03F7/70633

Abstract: Apparatus, method and computer program product for reducing overlay errors during a semiconductor photolithographic mask design process flow. The method obtains data representing density characteristics of a photo mask layout design; predicts stress induced displacements based on said obtained density characteristics data; and corrects the mask layout design data by specifying shift movement of individual photo mask design shapes to pre-compensate for predicted displacements. To obtain data representing density characteristics, the method merges pieces of data that are combined to make a photo mask to obtain a full reticle field data set. The merge includes a merge of data representing density characteristic driven stress effects. The density characteristics data for the merged reticle data are then computed. To predict stress-induced displacements, the method inputs said density characteristics data into a programmed model that predicts displacements as a function of density, and outputs the predicted shift data.

Abstract translation: 用于在半导体光刻掩模设计工艺流程期间减少重叠误差的装置，方法和计算机程序产品。 该方法获得表示光掩模布局设计的密度特性的数据; 基于所获得的密度特征数据预测应力诱导位移; 并通过指定各个照片掩模设计形状的移位移动来预测补偿预测的位移来校正掩模布局设计数据。 为了获得表示密度特性的数据，该方法合并组合的数据以制作光掩模以获得完整的掩模版场数据集。 合并包括表示密度特征驱动应力效应的数据的合并。 然后计算合并的掩模版数据的密度特性数据。 为了预测应力引起的位移，该方法将所述密度特征数据输入到预测作为密度的函数的位移的编程模型中，并输出预测的移位数据。

公开(公告)号：US09311442B2

公开(公告)日：2016-04-12

申请号：US14261632

申请日：2014-04-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shayak Banerjee ,  James A. Culp ,  Ian P. Stobert

IPC: G06F17/50 ,  G03F1/36 ,  G03F7/20

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F7/70441 ,  G06F17/5068 ,  G06F2217/12

Abstract: Various embodiments include computer-implemented methods, computer program products and systems for verifying an integrated circuit (IC) layout. In some cases, approaches include a computer-implemented method of verifying an IC layout, the method including: obtaining data about a process variation band for at least one physical feature in the IC layout; determining voltage-based process variation band thresholds for the at least one physical feature in the IC layout; determining whether the process variation band for the at least one physical feature in the IC layout meets design specifications for the IC layout based upon the voltage-based process variation band thresholds for the at least one physical feature in the IC layout; and modifying the IC layout in response to a determination that the process variation band for the at least one physical feature does not meet the design specifications.

Abstract translation: 各种实施例包括用于验证集成电路（IC）布局的计算机实现的方法，计算机程序产品和系统。 在某些情况下，方法包括验证IC布局的计算机实现的方法，该方法包括：获得关于IC布局中的至少一个物理特征的过程变化频带的数据; 确定所述IC布局中的所述至少一个物理特征的基于电压的过程变化带阈值; 基于IC布局中的至少一个物理特征的基于电压的过程变化带阈值来确定IC布局中的至少一个物理特征的过程变化带是否符合IC布局的设计规范; 以及响应于所述至少一个物理特征的所述过程变化带不符合所述设计规范的确定来修改所述IC布局。