Synthesizing low mask error enhancement factor lithography solutions
    1.
    发明授权
    Synthesizing low mask error enhancement factor lithography solutions 有权
    合成低掩模误差增强因子光刻解决方案

    公开(公告)号:US09395622B2

    公开(公告)日:2016-07-19

    申请号:US14185506

    申请日:2014-02-20

    Abstract: In one embodiment, a source mask optimization (SMO) method is provided that includes controlling bright region efficiency during at least one optical domain step. The bright region efficiency being the proportion of the total transmitted light that is transferred to bright areas of a target pattern. The optical domain intermediate solution provided by the at least one optical domain step may then be binarized to obtain an initial spatial domain solution with a controlled MEEF (Mask Error Enhancement Factor). The MEEF is controlled during at least one spatial domain step that optimizes the initial spatial domain solution.

    Abstract translation: 在一个实施例中,提供了一种源掩码优化(SMO)方法,其包括在至少一个光域步骤期间控制亮区效率。 亮区效率是传输到目标图形的明亮区域的总透射光的比例。 然后可以将由至少一个光学域步骤提供的光域中间溶液二值化以获得具有受控MEEF(掩模误差增强因子)的初始空间域解。 在至少一个优化初始空间域解决方案的空间域步骤中控制MEEF。

    Semiconductor fabrication design rule loophole checking for design for manufacturability optimization

    公开(公告)号:US10585346B2

    公开(公告)日:2020-03-10

    申请号:US15819213

    申请日:2017-11-21

    Abstract: Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.

    Semiconductor fabrication design rule loophole checking for design for manufacturability optimization

    公开(公告)号:US10394116B2

    公开(公告)日:2019-08-27

    申请号:US15696505

    申请日:2017-09-06

    Abstract: Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.

Patent Agency Ranking