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公开(公告)号：US09477550B2
公开(公告)日：2016-10-25
申请号：US14062856
申请日：2013-10-24
Applicant: GLOBALFOUNDRIES Inc.
Inventor： Benjiman L. Goodman , Luis A. Lastras-Montano , Eric E. Retter , Kenneth L. Wright
CPC classification number: G06F11/1076 , G06F11/10 , G06F11/1012 , G06F11/1048 , G06F11/1052 , G11C8/06 , G11C29/42 , G11C29/44 , G11C2029/0411
Abstract: A memory controller is equipped with multiple error correction circuits for different complexity levels of errors, but requested data is initially sent to a requesting unit (e.g., processor) via a bypass path which provides the lowest memory latency. The requesting unit performs error detection and, if an error is found, sends a retry select signal to the memory controller. The retry select signal provides an indication of which error correction unit should be used to provide complete correction of the error but add the minimum latency necessary. On the retry transmission, the controller uses the particular error correction unit indicated by the retry select signal. The memory controller can also have a persistent error detection circuit which identifies an address as being defective when an error is repeatedly indicated by multiple retry select signals, and the control logic can automatically transmits the requested data using the appropriate error correction unit.
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公开(公告)号：US09405468B2
公开(公告)日：2016-08-02
申请号：US14276025
申请日：2014-05-13
Applicant: GLOBALFOUNDRIES INC.
Inventor： Venkatraghavan Bringivijayaraghavan , Saurabh Chadha , Abhijit Saurabh , Saravanan Sethuraman , Kenneth L. Wright
IPC: G06F3/00 , G06F3/06 , G11C5/14 , G11C5/06 , G06F11/16 , G06F11/07 , G06F11/30 , G06F13/40 , G06F13/16 , G06F13/28 , G06F11/20
CPC classification number: G06F3/06 , G06F3/0617 , G06F3/0619 , G06F3/065 , G06F3/0659 , G06F3/0679 , G06F3/0688 , G06F11/0727 , G06F11/1666 , G06F11/20 , G06F11/2017 , G06F11/2092 , G06F11/3027 , G06F11/3034 , G06F13/1684 , G06F13/287 , G06F13/4068 , G11C5/06 , G11C5/148 , Y02D10/14 , Y02D10/151
Abstract: A system for memory device control may include a stacked memory device and a memory controller. The stacked memory device may include a stack of chips connected to a package substrate by electrical interconnects. The stack may include a plurality of memory chips, a primary control chip, and a secondary control chip. The primary and secondary control chips may be electrically connected to the plurality of memory chips by an internal data bus. The primary control chip may have logic to provide an interface between the internal data bus and a first external data bus. The secondary control chip may have logic to provide an interface between the internal data bus and a second external data bus.
Abstract translation: 用于存储器设备控制的系统可以包括堆叠的存储器设备和存储器控制器。 堆叠的存储器件可以包括通过电互连连接到封装衬底的芯片堆叠。 堆叠可以包括多个存储器芯片，主控制芯片和次级控制芯片。 主控制芯片和次控制芯片可以通过内部数据总线电连接到多个存储器芯片。 主控制芯片可以具有在内部数据总线和第一外部数据总线之间提供接口的逻辑。 辅助控制芯片可以具有在内部数据总线和第二外部数据总线之间提供接口的逻辑。
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3.发明授权公开(公告)号：US09436548B2
公开(公告)日：2016-09-06
申请号：US14098561
申请日：2013-12-06
Applicant: GLOBALFOUNDRIES Inc.
Inventor： Benjiman L. Goodman , Luis A. Lastras-Montano , Eric E. Retter , Kenneth L. Wright
CPC classification number: G06F11/1076 , G06F11/10 , G06F11/1012 , G06F11/1048 , G06F11/1052 , G11C8/06 , G11C29/42 , G11C29/44 , G11C2029/0411
Abstract: A memory controller is equipped with multiple error correction circuits for different complexity levels of errors, but requested data is initially sent to a requesting unit (e.g., processor) via a bypass path which provides the lowest memory latency. The requesting unit performs error detection and, if an error is found, sends a retry select signal to the memory controller. The retry select signal provides an indication of which error correction unit should be used to provide complete correction of the error but add the minimum latency necessary. On the retry transmission, the controller uses the particular error correction unit indicated by the retry select signal. The memory controller can also have a persistent error detection circuit which identifies an address as being defective when an error is repeatedly indicated by multiple retry select signals, and the control logic can automatically transmits the requested data using the appropriate error correction unit.
Abstract translation: 存储器控制器配备有用于不同复杂度错误水平的多个纠错电路，但是请求的数据最初经由提供最低存储器延迟的旁路路径发送到请求单元（例如，处理器）。 请求单元执行错误检测，并且如果发现错误，则将重试选择信号发送到存储器控制器。 重试选择信号提供了哪个错误校正单元应该用于提供错误的完整校正的指示，但是添加最小等待时间。 在重试传输中，控制器使用由重试选择信号指示的特定纠错单元。 存储器控制器还可以具有持续错误检测电路，其在由多个重试选择信号重复指示错误时将地址标识为有缺陷，并且控制逻辑可以使用适当的纠错单元自动发送所请求的数据。
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公开(公告)号：US09400602B2
公开(公告)日：2016-07-26
申请号：US14464090
申请日：2014-08-20
Applicant: GLOBALFOUNDRIES INC.
Inventor： Venkatraghavan Bringivijayaraghavan , Saurabh Chadha , Abhijit Saurabh , Saravanan Sethuraman , Kenneth L. Wright
IPC: G06F3/00 , G06F3/06 , G11C5/14 , G11C5/06 , G06F11/16 , G06F11/07 , G06F11/30 , G06F13/40 , G06F13/16 , G06F13/28 , G06F11/20
CPC classification number: G06F3/06 , G06F3/0617 , G06F3/0619 , G06F3/065 , G06F3/0659 , G06F3/0679 , G06F3/0688 , G06F11/0727 , G06F11/1666 , G06F11/20 , G06F11/2017 , G06F11/2092 , G06F11/3027 , G06F11/3034 , G06F13/1684 , G06F13/287 , G06F13/4068 , G11C5/06 , G11C5/148 , Y02D10/14 , Y02D10/151
Abstract: A system for memory device control may include a stacked memory device and a memory controller. The stacked memory device may include a stack of chips connected to a package substrate by electrical interconnects. The stack may include a plurality of memory chips, a primary control chip, and a secondary control chip. The primary and secondary control chips may be electrically connected to the plurality of memory chips by an internal data bus. The primary control chip may have logic to provide an interface between the internal data bus and a first external data bus. The secondary control chip may have logic to provide an interface between the internal data bus and a second external data bus.
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