METHODS OF GENERATING CIRCUIT LAYOUTS THAT ARE TO BE MANUFACTURED USING SADP ROUTING TECHNIQUES
    1.
    发明申请
    METHODS OF GENERATING CIRCUIT LAYOUTS THAT ARE TO BE MANUFACTURED USING SADP ROUTING TECHNIQUES 有权
    使用SADP路由技术生成要生产的电路的方法

    公开(公告)号:US20150113484A1

    公开(公告)日:2015-04-23

    申请号:US14578717

    申请日:2014-12-22

    CPC classification number: G06F17/5081 G03F1/70 G06F17/5068

    Abstract: One method disclosed herein involves, among other things, generating a set of mandrel mask rules, block mask rules and a virtual, software-based non-mandrel-metal mask. The method also includes creating a set of virtual non-mandrel mask rules that is a replica of the mandrel mask rules, generating a set of metal routing design rules based upon the mandrel mask rules, the block mask rules and the virtual non-mandrel mask rules, generating the circuit routing layout based upon the metal routing design rules, decomposing the circuit routing layout into a mandrel mask pattern and a block mask pattern, generating a first set of mask data corresponding to the mandrel mask pattern, and generating a second set of mask data corresponding to the block mask pattern.

    Abstract translation: 本文公开的一种方法尤其涉及生成一组心轴掩模规则,块掩模规则和基于软件的虚拟金属掩模。 该方法还包括创建一组虚拟非心轴掩模规则,该规则是心轴掩模规则的副本,基于心轴掩模规则,块掩模规则和虚拟非心轴掩模生成一组金属路由设计规则 规则,基于金属路由设计规则生成电路布线布局,将电路路由布局分解为心轴掩模图案和块掩模图案,产生对应于心​​轴掩模图案的第一组掩模数据,以及生成第二组 对应于块掩模图案的掩模数据。

    Methods of generating circuit layouts that are to be manufactured using SADP routing techniques and virtual non-mandrel mask rules
    2.
    发明授权
    Methods of generating circuit layouts that are to be manufactured using SADP routing techniques and virtual non-mandrel mask rules 有权
    使用SADP路由技术和虚拟非心轴掩码规则生成电路布局的方法

    公开(公告)号:US08954913B1

    公开(公告)日:2015-02-10

    申请号:US14043251

    申请日:2013-10-01

    CPC classification number: G06F17/5081 G03F1/70 G06F17/5068

    Abstract: One method disclosed herein involves, among other things, generating a set of mandrel mask rules, block mask rules and a virtual, software-based non-mandrel-metal mask. The method also includes creating a set of virtual non-mandrel mask rules that is a replica of the mandrel mask rules, generating a set of metal routing design rules based upon the mandrel mask rules, the block mask rules and the virtual non-mandrel mask rules, generating the circuit routing layout based upon the metal routing design rules, decomposing the circuit routing layout into a mandrel mask pattern and a block mask pattern, generating a first set of mask data corresponding to the mandrel mask pattern, and generating a second set of mask data corresponding to the block mask pattern.

    Abstract translation: 本文公开的一种方法尤其涉及生成一组心轴掩模规则,块掩模规则和基于软件的虚拟金属掩模。 该方法还包括创建一组虚拟非心轴掩模规则,该规则是心轴掩模规则的副本,基于心轴掩模规则,块掩模规则和虚拟非心轴掩模生成一组金属路由设计规则 规则,基于金属路由设计规则生成电路布线布局,将电路路由布局分解为心轴掩模图案和块掩模图案,产生对应于心​​轴掩模图案的第一组掩模数据,以及生成第二组 对应于块掩模图案的掩模数据。

    Methods of generating circuit layouts that are to be manufactured using SADP routing techniques

    公开(公告)号:US09613177B2

    公开(公告)日:2017-04-04

    申请号:US14578717

    申请日:2014-12-22

    CPC classification number: G06F17/5081 G03F1/70 G06F17/5068

    Abstract: One method disclosed herein involves, among other things, generating a set of mandrel mask rules, block mask rules and a virtual, software-based non-mandrel-metal mask. The method also includes creating a set of virtual non-mandrel mask rules that is a replica of the mandrel mask rules, generating a set of metal routing design rules based upon the mandrel mask rules, the block mask rules and the virtual non-mandrel mask rules, generating the circuit routing layout based upon the metal routing design rules, decomposing the circuit routing layout into a mandrel mask pattern and a block mask pattern, generating a first set of mask data corresponding to the mandrel mask pattern, and generating a second set of mask data corresponding to the block mask pattern.

    Color-insensitive rules for routing structures
    4.
    发明授权
    Color-insensitive rules for routing structures 有权
    路由结构的颜色不敏感规则

    公开(公告)号:US09158879B2

    公开(公告)日:2015-10-13

    申请号:US14017594

    申请日:2013-09-04

    CPC classification number: G06F17/5077

    Abstract: Methodologies and an apparatus enabling a generation of color undeterminable polygons in IC designs are disclosed. Embodiments include: determining a plurality of first routes extending horizontally in an IC design, each of the plurality of first routes being placed on one of a plurality of equally spaced vertical positions of the IC design; determining whether a second route overlaps one of the vertical positions of the plurality of equally spaced vertical positions; and selecting a design rule for the second route based on the determination of whether the second route overlaps.

    Abstract translation: 公开了在IC设计中能够产生颜色不可确定的多边形的方法和装置。 实施例包括:确定在IC设计中水平延伸的多个第一路线,所述多条第一路线中的​​每条路线被放置在所述IC设计的多个相等间隔的垂直位置之一上; 确定第二路线是否与所述多个等间隔垂直位置的垂直位置之一重叠; 以及基于所述第二路由是否重叠的确定来选择所述第二路由的设计规则。

    Color-insensitive rules for routing structures

    公开(公告)号:US09400863B2

    公开(公告)日:2016-07-26

    申请号:US14687477

    申请日:2015-04-15

    CPC classification number: G06F17/5077

    Abstract: Methodologies and an apparatus enabling a generation of color undeterminable polygons in IC designs are disclosed. Embodiments include: determining a plurality of first routes extending horizontally in an IC design, each of the plurality of first routes being placed on one of a plurality of equally spaced vertical positions of the IC design; determining whether a second route overlaps one of the vertical positions of the plurality of equally spaced vertical positions; and selecting a design rule for the second route based on the determination of whether the second route overlaps.

    Methods of forming a circuit that includes a cross-coupling gate contact structure wherein the circuit is to be manufactured using a triple patterning process
    6.
    发明授权
    Methods of forming a circuit that includes a cross-coupling gate contact structure wherein the circuit is to be manufactured using a triple patterning process 有权
    形成包括交叉耦合栅极接触结构的电路的方法,其中电路将使用三重图案化工艺制造

    公开(公告)号:US08969199B1

    公开(公告)日:2015-03-03

    申请号:US14054251

    申请日:2013-10-15

    Abstract: One illustrative method disclosed herein includes, among other things, patterning a hard mask layer using three patterned photoresist etch masks, wherein a first feature corresponding to a portion, but not all, of a cross-coupling gate contact structure is present in a first of the three patterned photoresist etch masks and a second feature corresponding to a portion, but not all, of the cross-coupling gate contact structure is present in a second or a third of the three patterned photoresist etch masks, patterning a layer of insulating material using the patterned hard mask layer as an etch mask, and forming a cross-coupling gate contact structure in a trench in the layer of insulating material.

    Abstract translation: 本文公开的一种说明性方法包括使用三种图案化的光致抗蚀剂蚀刻掩模图案化硬掩模层,其中对应于交叉耦合栅极接触结构的一部分但不是全部的第一特征存在于第一 三个图案化的光致抗蚀剂蚀刻掩模和对应于交叉耦合栅极接触结构的一部分但不是全部的第二特征存在于三个图案化的光致抗蚀剂蚀刻掩模的第二或第三个中,使用 图案化的硬掩模层作为蚀刻掩模,并且在绝缘材料层中的沟槽中形成交叉耦合栅极接触结构。

Patent Agency Ranking