公开(公告)号：US09972620B2

公开(公告)日：2018-05-15

申请号：US15234762

申请日：2016-08-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Charan V. Surisetty ,  Dominic J. Schepis ,  Kangguo Cheng ,  Alexander Reznicek

IPC: H01L21/28 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/3105 ,  H01L29/417

CPC classification number: H01L27/0886 ,  H01L21/31053 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/41791

Abstract: Electrical shorting between source and/or drain contacts and a conductive gate of a FinFET-based semiconductor structure are prevented by forming the source and drain contacts in two parts, a bottom contact part extending up to a height of the gate cap and an upper contact part situated on at least part of the bottom contact part.

公开(公告)号：US09728626B1

公开(公告)日：2017-08-08

申请号：US15251435

申请日：2016-08-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dominic J. Schepis ,  Charan V. Surisetty ,  Kangguo Cheng ,  Alexander Reznicek

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L29/32 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/02636 ,  H01L21/30604 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/32 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/785

Abstract: A FinFET includes a fin and a conductive gate surrounding a top channel region of the fin, the channel region of the fin being filled with an epitaxial semiconductor channel material extending below a bottom surface of the conductive gate. The top channel region of the fin includes epitaxial semiconductor channel material that is at least majority defect free, the at least a majority of defects associated with forming the epitaxial semiconductor material in the channel region being trapped below a top portion of the channel region. The FinFET may be achieved by a method, the method including providing a starting semiconductor structure, the starting semiconductor structure including a bulk semiconductor substrate, semiconductor fin(s) on the bulk semiconductor substrate and surrounded by a dielectric layer, and a dummy gate over a channel region of the semiconductor fin(s). The method further includes forming source and drain recesses adjacent the channel region, removing the dummy gate, recessing the semiconductor fin(s), the recessing leaving a fin opening above the recessed semiconductor fin(s), and growing epitaxial semiconductor channel material in the fin opening, such that at least a majority of defects associated with the growing are trapped at a bottom portion of the at least one fin opening.

公开(公告)号：US20150111373A1

公开(公告)日：2015-04-23

申请号：US14057357

申请日：2013-10-18

Applicant: GLOBALFOUNDRIES, INC. ,  International Business Machines Corporation

Inventor： William J. Cote ,  Laertis Economikos ,  Shom Ponoth ,  Theodorus E. Standaert ,  Charan V. Surisetty ,  Ruilong Xie

IPC: H01L21/8238 ,  H01L21/8234

CPC classification number: H01L21/823828 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823864

Abstract: A method of forming transistors is provided. The method includes forming a plurality of transistor structures to have a plurality of dummy gates on a substrate. Each dummy gate is surrounded by sidewall spacers of a height, which is less than the dummy gate and is different for different transistor structures resulting in divots of different depths above the sidewall spacers. The method then deposits a conformal dielectric layer on top of the dummy gates and inside the divots of the plurality of transistor structures with the conformal dielectric layer having a thickness of at least half of a width of the divots, removes only a portion of the conformal dielectric layer that is on top of the dummy gates to expose the dummy gates; and replaces the dummy gates with a plurality of high-k metal gates.

Abstract translation: 提供一种形成晶体管的方法。 该方法包括形成多个晶体管结构以在衬底上具有多个虚拟栅极。 每个虚拟栅极被高度的侧壁间隔物包围，该间隙小于虚拟栅极，并且对于不同的晶体管结构是不同的，导致在侧壁间隔物上方具有不同深度的裂缝。 该方法然后在保持电介质层的厚度至少为纹理宽度的一半之上的情况下，在虚拟栅极的顶部和多个晶体管结构的纹间之内沉积保形介电层，仅去除一部分保形 位于伪栅极顶部以暴露伪栅极的介电层; 并且用多个高k金属栅极代替伪栅极。