METHODS FOR FABRICATING FINFET INTEGRATED CIRCUITS WITH SIMULTANEOUS FORMATION OF LOCAL CONTACT OPENINGS
    1.
    发明申请
    METHODS FOR FABRICATING FINFET INTEGRATED CIRCUITS WITH SIMULTANEOUS FORMATION OF LOCAL CONTACT OPENINGS 有权
    同时形成局部接触开口的FINFET集成电路的制作方法

    公开(公告)号:US20150214113A1

    公开(公告)日:2015-07-30

    申请号:US14164582

    申请日:2014-01-27

    Abstract: A method for fabricating a finFET integrated circuit includes providing a finFET integrated circuit structure including a fin structure, a replacement metal gate structure having a silicon nitride cap disposed over and in contact with the fin structure, a contact structure including a tungsten material also disposed over and in contact with the fin structure, and an insulating layer disposed over the replacement metal gate structure and the contact structure. The method further includes forming a first opening in the insulating layer over the replacement gate structure and a second opening in the insulating layer over the contact structure. Forming the first and second openings includes exposing the FinFET integrated circuit structure to a single extreme ultraviolet lithography patterning. Still further, the method includes removing a portion of the silicon nitride material of the replacement metal gate structure and forming a metal fill material in the first and second openings.

    Abstract translation: 一种用于制造finFET集成电路的方法包括提供finFET集成电路结构,其包括翅片结构,具有设置在翅片结构上并与翅片结构接触的氮化硅盖的替换金属栅极结构,包括钨材料的接触结构也布置在 并且与翅片结构接触,以及设置在替换金属栅极结构和接触结构之上的绝缘层。 所述方法还包括在所述绝缘层上形成位于所述替代栅极结构上的第一开口和在所述接触结构上的所述绝缘层中的第二开口。 形成第一和第二开口包括将FinFET集成电路结构暴露于单个极紫外光刻图案。 此外,该方法包括去除替代金属栅极结构的一部分氮化硅材料并在第一和第二开口中形成金属填充材料。

    ASYMMETRIC OVERLAY MARK FOR OVERLAY MEASUREMENT

    公开(公告)号:US20190363053A1

    公开(公告)日:2019-11-28

    申请号:US15985838

    申请日:2018-05-22

    Abstract: One illustrative example of an overlay mark disclosed herein includes four quadrants (I-IV). Each quadrant of the mark contains an inner periodic structure and an outer periodic structure. Each of the outer periodic structures includes a plurality of outer features. Each of the inner periodic structures includes a plurality of first inner groups, each of the first inner groups having a plurality of first inner features, each first inner group being oriented such that there is an end-to-end spacing relationship between each first inner group and a selected one of the outer features.

    Asymmetric overlay mark for overlay measurement

    公开(公告)号:US10707175B2

    公开(公告)日:2020-07-07

    申请号:US15985838

    申请日:2018-05-22

    Abstract: One illustrative example of an overlay mark disclosed herein includes four quadrants (I-IV). Each quadrant of the mark contains an inner periodic structure and an outer periodic structure. Each of the outer periodic structures includes a plurality of outer features. Each of the inner periodic structures includes a plurality of first inner groups, each of the first inner groups having a plurality of first inner features, each first inner group being oriented such that there is an end-to-end spacing relationship between each first inner group and a selected one of the outer features.

    Methods for fabricating FinFET integrated circuits with simultaneous formation of local contact openings
    5.
    发明授权
    Methods for fabricating FinFET integrated circuits with simultaneous formation of local contact openings 有权
    用于同时形成局部接触开口的FinFET集成电路的制造方法

    公开(公告)号:US09397004B2

    公开(公告)日:2016-07-19

    申请号:US14164582

    申请日:2014-01-27

    Abstract: A method for fabricating a finFET integrated circuit includes providing a finFET integrated circuit structure including a fin structure, a replacement metal gate structure having a silicon nitride cap disposed over and in contact with the fin structure, a contact structure including a tungsten material also disposed over and in contact with the fin structure, and an insulating layer disposed over the replacement metal gate structure and the contact structure. The method further includes forming a first opening in the insulating layer over the replacement gate structure and a second opening in the insulating layer over the contact structure. Forming the first and second openings includes exposing the FinFET integrated circuit structure to a single extreme ultraviolet lithography patterning. Still further, the method includes removing a portion of the silicon nitride material of the replacement metal gate structure and forming a metal fill material in the first and second openings.

    Abstract translation: 一种用于制造finFET集成电路的方法包括提供finFET集成电路结构,其包括翅片结构,具有设置在翅片结构上并与翅片结构接触的氮化硅盖的替换金属栅极结构,包括钨材料的接触结构也布置在 并且与翅片结构接触,以及设置在替换金属栅极结构和接触结构之上的绝缘层。 所述方法还包括在所述绝缘层上形成位于所述替代栅极结构上的第一开口和在所述接触结构上的所述绝缘层中的第二开口。 形成第一和第二开口包括将FinFET集成电路结构暴露于单个极紫外光刻图案。 此外,该方法包括去除替代金属栅极结构的一部分氮化硅材料并在第一和第二开口中形成金属填充材料。

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