公开(公告)号：US10373877B1

公开(公告)日：2019-08-06

申请号：US15986390

申请日：2018-05-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haiting Wang ,  Hong Yu ,  Hui Zang ,  Wei Zhao ,  Yue Zhong ,  Guowei Xu ,  Laertis Economikos ,  Jerome Ciavatti ,  Scott Beasor

IPC: H01L21/8234 ,  H01L21/311 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L27/108 ,  H01L21/762 ,  H01L27/12 ,  H01L21/84

Abstract: One illustrative method disclosed herein includes forming a plurality of transistors on a semiconductor substrate, wherein each of the transistors comprise source/drain epitaxial semiconductor material in the source/drain regions, a contact etch stop layer (CESL) positioned above the source/drain epitaxial semiconductor material and an insulating material positioned above the contact etch stop layer, and forming a plurality of contact isolation cavities by performing at least one etching process sequence, wherein the etching process sequence is adapted to sequentially remove the insulating material, the CESL and the source/drain epitaxial semiconductor material, and forming a contact isolation structure in each of the contact isolation cavities. In this example, the method also includes, after forming the contact isolation structures, removing the sacrificial gate structures so as to form a plurality of replacement gate cavities, and forming a final gate structure in each of the plurality of replacement gate cavities.

公开(公告)号：US20190097019A1

公开(公告)日：2019-03-28

申请号：US15712748

申请日：2017-09-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Zhao ,  Haiting Wang ,  David P. Brunco ,  Jiehui Shu ,  Shesh Mani Pandey ,  Jinping Liu ,  Scott Beasor

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/417 ,  H01L21/762

CPC classification number: H01L29/6681 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/02664 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/41791 ,  H01L29/66795

Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.

公开(公告)号：US09419082B2

公开(公告)日：2016-08-16

申请号：US14259726

申请日：2014-04-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shiv Kumar Mishra ,  Zhiqing Li ,  Scott Beasor ,  Shesh Mani Pandey

IPC: H01L21/22 ,  H01L29/36 ,  H01L29/16 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/365 ,  H01L21/02532 ,  H01L21/02579 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/78

Abstract: P-type metal-oxide semiconductor field-effect transistors (pMOSFET's), semiconductor devices comprising the pMOSFET's, and methods of forming pMOSFET's are provided. The pMOSFET's include a silicon-germanium (SiGe) film that has a lower interface in contact with a semiconductor substrate and an upper surface, and the SiGe film has a graded boron doping profile where boron content increases upwardly over a majority of the width of boron-doped SiGe film between the lower interface of the SiGe film and the upper surface of the SiGe film. Methods of forming the pMOSFET's include: providing a semiconductor substrate; depositing a SiGe film on the semiconductor substrate, thereby forming a lower interface of the SiGe film in contact with the semiconductor substrate, and an upper surface of the SiGe film; and doping the SiGe film with boron to form a SiGe film having a graded boron doping profile where boron content increases upwardly over a majority of the width of boron-doped SiGe film between the lower interface of the SiGe film and the upper surface of the SiGe film.

Abstract translation: 提供了P型金属氧化物半导体场效应晶体管（pMOSFET），包括pMOSFET的半导体器件和形成pMOSFET的方法。 pMOSFET包括具有与半导体衬底和上表面接触的较低界面的硅 - 锗（SiGe）膜，并且SiGe膜具有梯度硼掺杂分布，其中硼含量在硼的宽度的大部分上向上增加 SiGe膜的下界面与SiGe膜的上表面之间的掺杂SiGe膜。 形成pMOSFET的方法包括：提供半导体衬底; 在半导体衬底上沉积SiGe膜，从而形成与半导体衬底接触的SiGe膜的下界面和SiGe膜的上表面; 并且用硼掺杂SiGe膜以形成具有渐变硼掺杂分布的SiGe膜，其中硼含量在SiGe膜的下界面和SiGe的上表面之间的硼掺杂SiGe膜的宽度的大部分上向上增加 电影。

公开(公告)号：US20200168731A1

公开(公告)日：2020-05-28

申请号：US16776807

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Chung Foong Tan ,  Guowei Xu ,  Haiting Wang ,  Yue Zhong ,  Ruilong Xie ,  Tek Po Rinus Lee ,  Scott Beasor

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/306 ,  H01L21/768 ,  H01L29/08

Abstract: An integrated circuit product is disclosed that includes a transistor device that includes a final gate structure, a gate cap, a low-k sidewall spacer positioned on and in contact with opposing sidewalls of the final gate structure, first and second contact etch stop layers (CESLs) located on opposite sides of the final gate structure, whereby the CESLs are positioned on and in contact with the low-k sidewall spacer, and a high-k spacer located on opposite sides of the final gate structure, wherein the high-k spacer is positioned in recesses formed in an upper portion of the CESLs.

公开(公告)号：US20190393321A1

公开(公告)日：2019-12-26

申请号：US16014076

申请日：2018-06-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guowei Xu ,  Hui Zang ,  Haiting Wang ,  Scott Beasor

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768

Abstract: Various processes form different structures including exemplary apparatuses that include (among other components) a first layer having channel regions, source/drain structures in the first layer on opposite sides of the channel regions, a gate insulator on the channel region, and a gate stack on the gate insulator. The gate stack can include a gate conductor, and a stack insulator or a gate contact on the gate conductor. The gate stack has lower sidewalls adjacent to the source/drain structures and upper sidewalls distal to the source/drain structures. Further, lower spacers are between the source/drain contacts and the lower sidewalls of the gate stack; and upper spacers between the source/drain contacts and the upper sidewalls of the gate stack. In some structures, the upper spacers can partially overlap the lower spacers.

公开(公告)号：US20190273148A1

公开(公告)日：2019-09-05

申请号：US16415519

申请日：2019-05-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Zhao ,  Haiting Wang ,  David P. Brunco ,  Jiehui Shu ,  Shesh Mani Pandey ,  Jinping Liu ,  Scott Beasor

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/762 ,  H01L29/417

Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.

公开(公告)号：US09984933B1

公开(公告)日：2018-05-29

申请号：US15723416

申请日：2017-10-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yiheng Xu ,  Haiting Wang ,  Wei Zhao ,  Todd B. Abrams ,  Jiehui Shu ,  Jinping Liu ,  Scott Beasor

IPC: H01L21/311 ,  H01L21/8234 ,  H01L21/306 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L21/823431 ,  H01L21/28123 ,  H01L21/30625 ,  H01L21/823481 ,  H01L29/785

Abstract: A hardmask is patterned on a first material to leave hardmask elements. The first material is patterned into fins through the hardmask. A layer of silicon is formed on the hardmask elements and the fins in processing that forms the layer of silicon thicker on the hardmask elements relative to the fins. An isolation material is formed on the layer of silicon to leave the isolation material filling spaces between the fins. The isolation material and the layer of silicon are annealed to consume relatively thinner portions of the layer of silicon and leave the layer of silicon on the hardmask elements as silicon elements. A chemical mechanical polishing (CMP) is performed on the isolation material to make the isolation material planar with the silicon elements. A first etching agent removes the silicon elements on the hardmask elements, and a second chemical agent removes the hardmask elements.

公开(公告)号：US20150214113A1

公开(公告)日：2015-07-30

申请号：US14164582

申请日：2014-01-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Guillaume Bouche ,  Erik Geiss ,  Scott Beasor ,  Andy Wei ,  Deniz Elizabeth Civay

IPC: H01L21/8234 ,  H01L29/16 ,  H01L21/311 ,  H01L21/027 ,  H01L21/768 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L21/823431 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/845 ,  H01L23/485 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/785

Abstract: A method for fabricating a finFET integrated circuit includes providing a finFET integrated circuit structure including a fin structure, a replacement metal gate structure having a silicon nitride cap disposed over and in contact with the fin structure, a contact structure including a tungsten material also disposed over and in contact with the fin structure, and an insulating layer disposed over the replacement metal gate structure and the contact structure. The method further includes forming a first opening in the insulating layer over the replacement gate structure and a second opening in the insulating layer over the contact structure. Forming the first and second openings includes exposing the FinFET integrated circuit structure to a single extreme ultraviolet lithography patterning. Still further, the method includes removing a portion of the silicon nitride material of the replacement metal gate structure and forming a metal fill material in the first and second openings.

Abstract translation: 一种用于制造finFET集成电路的方法包括提供finFET集成电路结构，其包括翅片结构，具有设置在翅片结构上并与翅片结构接触的氮化硅盖的替换金属栅极结构，包括钨材料的接触结构也布置在 并且与翅片结构接触，以及设置在替换金属栅极结构和接触结构之上的绝缘层。 所述方法还包括在所述绝缘层上形成位于所述替代栅极结构上的第一开口和在所述接触结构上的所述绝缘层中的第二开口。 形成第一和第二开口包括将FinFET集成电路结构暴露于单个极紫外光刻图案。 此外，该方法包括去除替代金属栅极结构的一部分氮化硅材料并在第一和第二开口中形成金属填充材料。

公开(公告)号：US10763176B2

公开(公告)日：2020-09-01

申请号：US16668500

申请日：2019-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Scott Beasor ,  Haiting Wang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

Abstract: One illustrative device disclosed includes a gate structure and a sidewall spacer positioned adjacent the gate structure, the sidewall spacer having an upper surface, wherein an upper portion of the gate structure is positioned above a level of the upper surface of the sidewall spacer. In this illustrative example, the device also includes a tapered upper surface on the upper portion of the gate structure and a gate cap, the gate cap being positioned above the tapered upper surface of the gate structure and above the upper surface of the sidewall spacer.

公开(公告)号：US10707175B2

公开(公告)日：2020-07-07

申请号：US15985838

申请日：2018-05-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Zhao ,  Minghao Tang ,  Rui Chen ,  Dongyue Yang ,  Haiting Wang ,  Erik Geiss ,  Scott Beasor

IPC: H01L23/544

Abstract: One illustrative example of an overlay mark disclosed herein includes four quadrants (I-IV). Each quadrant of the mark contains an inner periodic structure and an outer periodic structure. Each of the outer periodic structures includes a plurality of outer features. Each of the inner periodic structures includes a plurality of first inner groups, each of the first inner groups having a plurality of first inner features, each first inner group being oriented such that there is an end-to-end spacing relationship between each first inner group and a selected one of the outer features.