公开(公告)号：US10078107B2

公开(公告)日：2018-09-18

申请号：US14924439

申请日：2015-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jaime Bravo ,  Vikrant Chauhan ,  Ryan Scott Smith

IPC: G01R31/26 ,  G01R31/28

CPC classification number: G01R31/2607 ,  G01R31/2601 ,  G01R31/2831 ,  G01R31/2884

Abstract: Three reference resistors of the same resistance and a test structure are connected in a circuit having a Wheatstone Bride design. The circuit is electrically coupled between an input and ground. A voltage applied at the input resulting in an electrical characteristic difference between two midpoints of the circuit indicates the need for corrective action with respect to a design of the test structure for either OPC or etch bias.

公开(公告)号：US10311186B2

公开(公告)日：2019-06-04

申请号：US15096551

申请日：2016-04-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jaime Bravo ,  Vikrant Chauhan ,  Piyush Pathak ,  Shobhit Malik ,  Uwe Paul Schroeder

IPC: G06F17/50

Abstract: Methodologies and a device for assessing integrated circuit and pattern for yield risk based on 3D simulation of semiconductor patterns are provided. Embodiments include generating, with a processor, a 3D simulation of semiconductor patterns; obtaining critical dimensions of distances between layers or within a layer of the 3D simulation of semiconductor patterns; comparing the set of critical dimensions with predefined minimum dimensions; and yield scoring each of the semiconductor patterns of the 3D simulation based on the comparing step.