公开(公告)号：US20180341739A1

公开(公告)日：2018-11-29

申请号：US15602810

申请日：2017-05-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Uwe Paul Schroeder ,  Fadi Batarseh ,  Karthik Krishnamoorthy ,  Ahmed Omran

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: An identification of a first area of an IC design surrounding a failure component is received; and, in response, a smaller portion of the first area is selected. The smaller portion also surrounds the failure component, is smaller than the first area, and contains less circuit components than the first area. The smaller portion is matched to other areas of the IC design to identify potentially undesirable patterns of the IC design that are the same size as the first area. Additionally, the potentially undesirable patterns are grouped into pattern categories, the pattern categories are matched to known good pattern categories, and the known good patterns are removed from the potentially undesirable patterns to leave potential failure patterns. The potential failure patterns of the IC design are then output.

公开(公告)号：US09547741B2

公开(公告)日：2017-01-17

申请号：US14518939

申请日：2014-10-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Uwe Paul Schroeder ,  Sushama Davar

IPC: G06F17/50 ,  H01L29/06 ,  H01L29/66

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/02 ,  G06F2217/06 ,  H01L29/0661 ,  H01L29/6681

Abstract: At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device. A design for an integrated circuit device is received; The design comprises a first functional cell and a second functional cell. The first functional cell is placed on a circuit layout. A determination is made as to whether the first cell comprises a vertical boundary that is electrically floating. A filler cell is placed adjacent to the vertical boundary on the circuit layout in response to determining that the first cell comprises the vertical boundary that is electrically floating. The second functional cell is placed adjacent to the filler cell to form a contiguous active area on the circuit layout.

Abstract translation: 所公开的至少一种方法，装置和系统涉及用于集成电路装置的电路布局。 接收集成电路装置的设计; 该设计包括第一功能单元和第二功能单元。 第一个功能单元放置在电路布局上。 确定第一单元是否包括电浮动的垂直边界。 响应于确定第一单元包括电浮动的垂直边界，填充单元被放置在电路布局上的垂直边界附近。 第二功能单元被放置成与填充单元相邻以在电路布局上形成连续的有效区域。

公开(公告)号：US10248754B2

公开(公告)日：2019-04-02

申请号：US15602810

申请日：2017-05-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Uwe Paul Schroeder ,  Fadi Batarseh ,  Karthik Krishnamoorthy ,  Ahmed Omran

IPC: G06F17/50

Abstract: An identification of a first area of an IC design surrounding a failure component is received; and, in response, a smaller portion of the first area is selected. The smaller portion also surrounds the failure component, is smaller than the first area, and contains less circuit components than the first area. The smaller portion is matched to other areas of the IC design to identify potentially undesirable patterns of the IC design that are the same size as the first area. Additionally, the potentially undesirable patterns are grouped into pattern categories, the pattern categories are matched to known good pattern categories, and the known good patterns are removed from the potentially undesirable patterns to leave potential failure patterns. The potential failure patterns of the IC design are then output.

公开(公告)号：US20160110489A1

公开(公告)日：2016-04-21

申请号：US14518939

申请日：2014-10-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Uwe Paul Schroeder ,  Sushama Davar

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/02 ,  G06F2217/06 ,  H01L29/0661 ,  H01L29/6681

Abstract: At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device. A design for an integrated circuit device is received; The design comprises a first functional cell and a second functional cell. The first functional cell is placed on a circuit layout. A determination is made as to whether the first cell comprises a vertical boundary that is electrically floating. A filler cell is placed adjacent to the vertical boundary on the circuit layout in response to determining that the first cell comprises the vertical boundary that is electrically floating. The second functional cell is placed adjacent to the filler cell to form a contiguous active area on the circuit layout.

Abstract translation: 所公开的至少一种方法，装置和系统涉及用于集成电路装置的电路布局。 接收集成电路装置的设计; 该设计包括第一功能单元和第二功能单元。 第一个功能单元放置在电路布局上。 确定第一单元是否包括电浮动的垂直边界。 响应于确定第一单元包括电浮动的垂直边界，填充单元被放置在电路布局上的垂直边界附近。 第二功能单元被放置成与填充单元相邻以在电路布局上形成连续的有效区域。

公开(公告)号：US10311186B2

公开(公告)日：2019-06-04

申请号：US15096551

申请日：2016-04-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jaime Bravo ,  Vikrant Chauhan ,  Piyush Pathak ,  Shobhit Malik ,  Uwe Paul Schroeder

IPC: G06F17/50

Abstract: Methodologies and a device for assessing integrated circuit and pattern for yield risk based on 3D simulation of semiconductor patterns are provided. Embodiments include generating, with a processor, a 3D simulation of semiconductor patterns; obtaining critical dimensions of distances between layers or within a layer of the 3D simulation of semiconductor patterns; comparing the set of critical dimensions with predefined minimum dimensions; and yield scoring each of the semiconductor patterns of the 3D simulation based on the comparing step.

公开(公告)号：US10055535B2

公开(公告)日：2018-08-21

申请号：US15277796

申请日：2016-09-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Piyush Pathak ,  Robert C. Pack ,  Wei-Long Wang ,  Karthik Krishnamoorthy ,  Fadi S. Batarseh ,  Uwe Paul Schroeder ,  Sriram Madhavan

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F7/70433 ,  G06F17/5036 ,  G06F2217/12 ,  Y02P90/265

Abstract: Disclosed is a method and corresponding system and program product that includes providing integrated circuit design layout(s), deconstructing the integrated circuit design layout(s) into unit-level geometric constructs, identifying anomalies in the unit-level geometric constructs, and storing anomaly data in a database. The method further includes determining one or more feature attributes for each of the plurality of unit-level geometric constructs, annotating the unit-level geometric constructs with feature attributes, resulting in annotated unit-level geometric constructs, mapping the annotated unit-level geometric constructs in a hyperplane formed by one or more feature attributes, each of the one or more feature attributes forming a dimensional axis of the hyperplane, resulting in a mapped hyperplane, applying a first model to the mapped hyperplane, identifying the anomalies from applying the first model, and applying a second model to the mapped hyperplane to rank the anomalies for printability risk, the generated data including rank data.

公开(公告)号：US20160099239A1

公开(公告)日：2016-04-07

申请号：US14965639

申请日：2015-12-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Uwe Paul Schroeder ,  Sushama Davar

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L27/0207 ,  G06F17/5031 ,  G06F17/5081 ,  G06F2217/78 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/6681 ,  H01L29/785

Abstract: At least one method, apparatus and system disclosed herein involves performing power reduction process on a FinFET device. A first design is provided. The first design comprises a process mask definition, a FinFET device that comprises a plurality of fins characterized by said process mask, and a timing requirement relating to an operation of said FinFET device. A timing parameter of said operation of said FinFET device is determined. Based upon said timing parameter, a determination is made as to whether a drive capability of said FinFET device is above a level required to maintain said timing requirement. The process mask is modified for reducing at least one of said fins in response to said determining that said drive capability is above said level required to maintain said timing requirement.

Abstract translation: 本文公开的至少一种方法，装置和系统涉及在FinFET器件上进行功率降低处理。 提供了第一个设计。 第一设计包括处理掩模定义，FinFET器件，其包括由所述处理掩模表征的多个鳍片，以及与所述FinFET器件的操作相关的定时要求。 确定所述FinFET器件的所述操作的定时参数。 基于所述定时参数，确定所述FinFET器件的驱动能力是否高于维持所述定时要求所需的电平。 修改过程掩模以响应于所述确定所述驱动能力高于维持所述定时要求所需的水平的至少一个所述鳍片。

公开(公告)号：US10276674B2

公开(公告)日：2019-04-30

申请号：US15194682

申请日：2016-06-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Uwe Paul Schroeder

IPC: H01L29/00 ,  H01L29/417 ,  H01L29/66 ,  H01L29/49 ,  H01L21/768 ,  H01L29/78

Abstract: One illustrative method disclosed includes, among other things, forming a sacrificial S/D contact structure above an S/D region of a transistor device, removing at least a portion of a gate cap and at least a portion of a gate sidewall spacer to define a gate contact cavity that is positioned entirely above the active region and exposes an upper surface of a gate structure of the transistor device, and forming an internal sidewall spacer within the gate contact cavity. The method also includes performing at least one process operation to remove at least the sacrificial S/D contact structure and define a S/D contact cavity, and forming a gate contact structure within the gate contact cavity that is conductively coupled to the gate structure and forming a S/D contact structure within the S/D contact cavity that is conductively coupled to the S/D region.

公开(公告)号：US20170373161A1

公开(公告)日：2017-12-28

申请号：US15194682

申请日：2016-06-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Uwe Paul Schroeder

IPC: H01L29/417 ,  H01L21/768 ,  H01L29/49 ,  H01L29/66 ,  H01L21/311

CPC classification number: H01L29/41791 ,  H01L21/7684 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

Abstract: One illustrative method disclosed includes, among other things, forming a sacrificial S/D contact structure above an S/D region of a transistor device, removing at least a portion of a gate cap and at least a portion of a gate sidewall spacer to define a gate contact cavity that is positioned entirely above the active region and exposes an upper surface of a gate structure of the transistor device, and forming an internal sidewall spacer within the gate contact cavity. The method also includes performing at least one process operation to remove at least the sacrificial S/D contact structure and define a S/D contact cavity, and forming a gate contact structure within the gate contact cavity that is conductively coupled to the gate structure and forming a S/D contact structure within the S/D contact cavity that is conductively coupled to the S/D region.

公开(公告)号：US09245087B1

公开(公告)日：2016-01-26

申请号：US14473986

申请日：2014-08-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Uwe Paul Schroeder ,  Sushama Davar

IPC: G06F17/50 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L27/0207 ,  G06F17/5031 ,  G06F17/5081 ,  G06F2217/78 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/6681 ,  H01L29/785

Abstract: At least one method, apparatus and system disclosed herein involves performing power reduction process on a FinFET device. A first design is provided. The first design comprises a process mask definition, a FinFET device that comprises a plurality of fins characterized by said process mask, and a timing requirement relating to an operation of said FinFET device. A timing parameter of said operation of said FinFET device is determined. Based upon said timing parameter, a determination is made as to whether a drive capability of said FinFET device is above a level required to maintain said timing requirement. The process mask is modified for reducing at least one of said fins in response to said determining that said drive capability is above said level required to maintain said timing requirement.

Abstract translation: 本文公开的至少一种方法，装置和系统涉及在FinFET器件上进行功率降低处理。 提供了第一个设计。 第一设计包括处理掩模定义，FinFET器件，其包括由所述处理掩模表征的多个鳍片，以及与所述FinFET器件的操作相关的定时要求。 确定所述FinFET器件的所述操作的定时参数。 基于所述定时参数，确定所述FinFET器件的驱动能力是否高于维持所述定时要求所需的电平。 修改过程掩模以响应于所述确定所述驱动能力高于维持所述定时要求所需的水平的至少一个所述鳍片。