公开(公告)号：US10297675B1

公开(公告)日：2019-05-21

申请号：US15795879

申请日：2017-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alina Vinslava ,  Hsien-Ching Lo ,  Yongjun Shi ,  Jianwei Peng ,  Jianghu Yan ,  Yi Qi

IPC: H01L21/84 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/08

Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region in a semiconductor fin. The semiconductor fin is etched with a first etching process to form a first cavity extending into the semiconductor fin adjacent to the channel region. The semiconductor fin is etched with a second etching process to form a second cavity that is volumetrically smaller than the first cavity and that adjoins the first cavity.

公开(公告)号：US20190181243A1

公开(公告)日：2019-06-13

申请号：US16276045

申请日：2019-02-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alina Vinslava ,  Hsien-Ching Lo ,  Yongjun Shi ,  Jianwei Peng ,  Jianghu Yan ,  Yi Qi

IPC: H01L29/66 ,  H01L21/84 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165 ,  H01L29/16 ,  H01L21/3065 ,  H01L21/02 ,  H01L29/161

Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region in a semiconductor fin. The semiconductor fin is etched with a first etching process to form a first cavity extending into the semiconductor fin adjacent to the channel region. The semiconductor fin is etched with a second etching process to form a second cavity that is volumetrically smaller than the first cavity and that adjoins the first cavity.

公开(公告)号：US09159667B2

公开(公告)日：2015-10-13

申请号：US13951654

申请日：2013-07-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiaoqiang Zhang ,  O Sung Kwon ,  Jianghu Yan ,  Wen-Hu Hung ,  Roderick Miller ,  HongLiang Shen

IPC: H01L21/8238 ,  H01L23/525 ,  H01L21/768 ,  H01L27/06

CPC classification number: H01L23/5256 ,  H01L21/28518 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76855 ,  H01L27/0617 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An e-fuse device disclosed herein includes an anode and a cathode that are conductively coupled to the doped region formed in a substrate, wherein the anode includes a first metal silicide region positioned on the doped region and a first conductive metal-containing contact that is positioned above and coupled to the first metal silicide region, and the cathode includes a second metal silicide region positioned on the doped region and a second conductive metal-containing contact that is positioned above and conductively coupled to the second metal silicide region. A method disclosed herein includes forming a doped region in a substrate for an e-fuse device and performing at least one common process operation to form a first conductive structure on the doped region of the e-fuse device and a second conductive structure on a source/drain region of a transistor.

Abstract translation: 本文公开的电熔丝装置包括导电耦合到形成在衬底中的掺杂区域的阳极和阴极，其中阳极包括位于掺杂区域上的第一金属硅化物区域和第一导电金属接触层， 位于第一金属硅化物区域上方并且耦合到第一金属硅化物区域，并且阴极包括位于掺杂区域上的第二金属硅化物区域和位于第二金属硅化物区域之上并导电耦合到第二金属硅化物区域的第二导电金属接触点。 本文公开的方法包括在电子熔丝器件的衬底中形成掺杂区域，并且执行至少一个公共工艺操作以在电熔丝器件的掺杂区域上形成第一导电结构，并在源极上形成第二导电结构 /漏极区域。

公开(公告)号：US20190131433A1

公开(公告)日：2019-05-02

申请号：US15795879

申请日：2017-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alina Vinslava ,  Hsien-Ching Lo ,  Yongjun Shi ,  Jianwei Peng ,  Jianghu Yan ,  Yi Qi

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/78

Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region in a semiconductor fin. The semiconductor fin is etched with a first etching process to form a first cavity extending into the semiconductor fin adjacent to the channel region. The semiconductor fin is etched with a second etching process to form a second cavity that is volumetrically smaller than the first cavity and that adjoins the first cavity.

公开(公告)号：US20150340319A1

公开(公告)日：2015-11-26

申请号：US14817546

申请日：2015-08-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiaoqiang Zhang ,  O Sung Kwon ,  Jianghu Yan ,  Wen-Hu Hung ,  Roderick Miller ,  HongLiang Shen

IPC: H01L23/525

CPC classification number: H01L23/5256 ,  H01L21/28518 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76855 ,  H01L27/0617 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An e-fuse device disclosed herein includes an anode and a cathode that are conductively coupled to the doped region formed in a substrate, wherein the anode includes a first metal silicide region positioned on the doped region and a first conductive metal-containing contact that is positioned above and coupled to the first metal silicide region, and the cathode includes a second metal silicide region positioned on the doped region and a second conductive metal-containing contact that is positioned above and conductively coupled to the second metal silicide region. A method disclosed herein includes forming a doped region in a substrate for an e-fuse device and performing at least one common process operation to form a first conductive structure on the doped region of the e-fuse device and a second conductive structure on a source/drain region of a transistor.

Abstract translation: 本文公开的电熔丝装置包括导电耦合到形成在衬底中的掺杂区域的阳极和阴极，其中阳极包括位于掺杂区域上的第一金属硅化物区域和第一导电金属接触层， 位于第一金属硅化物区域上方并且耦合到第一金属硅化物区域，并且阴极包括位于掺杂区域上的第二金属硅化物区域和位于第二金属硅化物区域之上并导电耦合到第二金属硅化物区域的第二导电金属接触点。 本文公开的方法包括在电子熔丝器件的衬底中形成掺杂区域，并且执行至少一个公共工艺操作以在电熔丝器件的掺杂区域上形成第一导电结构，并在源极上形成第二导电结构 /漏极区域。