公开(公告)号：US20150169818A1

公开(公告)日：2015-06-18

申请号：US14132926

申请日：2013-12-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Swamy Muddu ,  Shangliang Jiang

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5077 ,  G06F2217/12 ,  G06F2217/72

Abstract: Via redundancy insertion is described. A via layout is analyzed by identifying each via, and for each via, identifying a location therefore in the layout, whether the via is redundant and a layout configuration for the via. Each via is classified into a bin of similar layout configurations. For each bin of redundant vias, possible via replacement candidates are determined from a database of possible replacement vias, and the candidates are ranked according to rule-based, recommendation-based and/or model-based criteria. For each via in each bin having a replacement(s), an optimal replacement is identified from among the ranked candidates taken in ranked order that first satisfies another criteria, such as not violating an applicable design rule. The layout is then updated with the optimal replacement.

Abstract translation: 描述了冗余插入。 通过识别每个通孔，并且对于每个通孔，分析识别布局中的位置，通孔是否冗余以及通孔的布局配置来分析通孔布局。 每个通孔被分类为类似布局配置的一个bin。 对于冗余通路的每个二进制箱，可以通过替换候选者从可能的替换通孔的数据库确定，并且根据基于规则的，基于推荐的和/或基于模型的准则对候选进行排名。 对于具有替换的每个仓中的每个通道，从首先满足另一标准的排序顺序中排除的排名候选者中确定最佳替换，例如不违反适用的设计规则。 然后使用最佳替换更新布局。

公开(公告)号：US09189589B2

公开(公告)日：2015-11-17

申请号：US14132926

申请日：2013-12-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Swamy Muddu ,  Shangliang Jiang

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5077 ,  G06F2217/12 ,  G06F2217/72

Abstract: Via redundancy insertion is described. A via layout is analyzed by identifying each via, and for each via, identifying a location therefore in the layout, whether the via is redundant and a layout configuration for the via. Each via is classified into a bin of similar layout configurations. For each bin of redundant vias, possible via replacement candidates are determined from a database of possible replacement vias, and the candidates are ranked according to rule-based, recommendation-based and/or model-based criteria. For each via in each bin having a replacement(s), an optimal replacement is identified from among the ranked candidates taken in ranked order that first satisfies another criteria, such as not violating an applicable design rule. The layout is then updated with the optimal replacement.

Abstract translation: 描述了冗余插入。 通过识别每个通孔，并且对于每个通孔，分析识别布局中的位置，通孔是否冗余以及通孔的布局配置来分析通孔布局。 每个通孔被分类为类似布局配置的一个bin。 对于冗余通路的每个二进制箱，可以通过替换候选者从可能的替换通孔的数据库确定，并且根据基于规则的，基于推荐的和/或基于模型的准则对候选进行排名。 对于具有替换的每个仓中的每个通道，从首先满足另一标准的排序顺序中排除的排名候选者中确定最佳替换，例如不违反适用的设计规则。 然后使用最佳替换更新布局。

公开(公告)号：US08869077B1

公开(公告)日：2014-10-21

申请号：US13901164

申请日：2013-05-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Rani Ghaida ,  Swamy Muddu

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

Abstract: Methodologies and an apparatus enabling an improvement of a manufacturing yield of an IC design are disclosed. Embodiments include: determining a portion of a layout of an IC design, the portion including a first pattern including a plurality of design connections; determining a function performed by the first pattern based, at least in part, on the design connections; and selecting, by a processor, a second pattern based on the function.

Abstract translation: 公开了能够提高IC设计的制造成品率的方法和装置。 实施例包括：确定IC设计的布局的一部分，该部分包括包括多个设计连接的第一图案; 至少部分地基于所述设计连接来确定由所述第一图案执行的功能; 以及基于所述功能，由处理器选择第二模式。

公开(公告)号：US08898606B1

公开(公告)日：2014-11-25

申请号：US14080866

申请日：2013-11-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Rani Abou Ghaida ,  Ahmed Mohyeldin ,  Piyush Pathak ,  Swamy Muddu ,  Vito Dai ,  Luigi Capodieci

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5077 ,  Y02T10/82

Abstract: A process and apparatus are provided for automated pattern-based semiconductor design layout correction. Embodiments include: determining a portion of a layout of an IC design, the portion comprising a first pattern of a plurality of routes connecting a plurality of design connections; determining one or more sets of the plurality of design connections based on the plurality of routes; and determining, by a processor, a second pattern of a plurality of routes connecting the plurality of design connections within the portion based on the one or more sets.

Abstract translation: 提供了一种用于基于自动图案的半导体设计布局校正的工艺和装置。 实施例包括：确定IC设计的布局的一部分，该部分包括连接多个设计连接的多条路线的第一模式; 基于所述多个路由确定所述多个设计连接的一个或多个集合; 以及由处理器确定基于所述一个或多个集合来连接所述部分内的所述多个设计连接的多条路线的第二模式。