公开(公告)号：US20240234533A1

公开(公告)日：2024-07-11

申请号：US18152710

申请日：2023-01-10

Applicant: GlobalFoundries U.S. Inc.

Inventor： Santosh Sharma ,  Shesh Mani Pandey ,  Rajendran Krishnasamy

IPC: H01L29/47 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/475 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

Abstract: Disclosed is a structure including a substrate and a transistor on the substrate. The transistor includes a barrier layer above the substrate and a multi-gate structure on the barrier layer. The multi-gate structure includes a primary gate and a secondary gate. The secondary gate has opposing sidewalls, opposing end walls and a top surface. The primary gate includes essentially vertically-oriented first portions on the barrier layer positioned laterally adjacent to opposing sidewalls, respectively, of the secondary gate. Optionally, the primary gate also includes an essentially horizontally-oriented second portion on the top surface of the secondary gate and/or essentially vertically-oriented third portions on the opposing end walls, respectively. The secondary gate can be a floating gate. Also disclosed is a method of forming the structure.

公开(公告)号：US20240088272A1

公开(公告)日：2024-03-14

申请号：US17931938

申请日：2022-09-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey ,  Vibhor Jain

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/735 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/6625

Abstract: Embodiments of the disclosure provide a bipolar transistor and gate structure on a semiconductor fin and methods to form the same. A structure according to the disclosure includes a semiconductor fin including an intrinsic base region and an extrinsic base region adjacent the intrinsic base region along a length of the semiconductor fin. Sidewalls of the intrinsic base region of the semiconductor fin are adjacent an emitter and a collector along a width of the semiconductor fin. A gate structure is on the semiconductor fin and between the intrinsic base region and the extrinsic base region.

公开(公告)号：US11923417B2

公开(公告)日：2024-03-05

申请号：US17692517

申请日：2022-03-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hong Yu ,  Shesh Mani Pandey

IPC: H01L29/10 ,  H01L21/8222 ,  H01L27/082 ,  H01L29/66 ,  H01L29/735 ,  H01L29/737

CPC classification number: H01L29/1008 ,  H01L29/6625 ,  H01L29/735 ,  H01L21/8222 ,  H01L27/082 ,  H01L29/737

Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a substrate having a well, a first terminal including a first raised semiconductor layer, a second terminal including a second raised semiconductor layer, and a base layer positioned in a lateral direction between the first raised semiconductor layer of the first terminal and the second raised semiconductor layer of the second terminal. The base layer has an overlapping arrangement with the well. The structure further includes a dielectric layer positioned in a vertical direction between the first terminal and the substrate, the second terminal and the substrate, and the base layer and the substrate.

公开(公告)号：US11869958B2

公开(公告)日：2024-01-09

申请号：US17745280

申请日：2022-05-16

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Judson R. Holt ,  Shesh Mani Pandey ,  Vibhor Jain

IPC: H01L29/737 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7371 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a collector in a semiconductor substrate; a subcollector in the semiconductor substrate; an intrinsic base over the subcollector; an extrinsic base adjacent to the intrinsic base; an emitter over the intrinsic base; and an isolation structure between the extrinsic base and the emitter and which overlaps the subcollector.

公开(公告)号：US20230420551A1

公开(公告)日：2023-12-28

申请号：US17849867

申请日：2022-06-27

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey ,  Souvick Mitra ,  Anindya Nath

IPC: H01L29/745 ,  H01L29/66

CPC classification number: H01L29/7455 ,  H01L29/66363

Abstract: Structures for a silicon-controlled rectifier and methods of forming a structure for a silicon-controlled rectifier. The structure comprises a semiconductor substrate, a dielectric layer on the semiconductor substrate, and a first well and a second well in the semiconductor substrate beneath the dielectric layer. The first well has a first conductivity type, the second well has a second conductivity type opposite to the first conductivity type, and the second well adjoins the first well along a p-n junction. The structure further comprises a first terminal and a second terminal above the dielectric layer, a first connection extending through the dielectric layer from the first terminal to the first well, and a second connection extending through the dielectric layer from the second terminal to the second well.

公开(公告)号：US20230244033A1

公开(公告)日：2023-08-03

申请号：US17588440

申请日：2022-01-31

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey ,  Yusheng Bian ,  Judson Holt

IPC: G02B6/136

CPC classification number: G02B6/136 ,  G02B2006/12061

Abstract: Waveguide structures and methods of fabricating a waveguide structure. The structure includes a first waveguide core, a second waveguide core, and a third waveguide core adjacent to the first waveguide core and the second waveguide core. The third waveguide core is laterally separated from the first waveguide core by a first slot, and the third waveguide core is laterally separated from the second waveguide core by a second slot. The first waveguide core and the second waveguide core comprise a first material, and the third waveguide core comprises a second material that is different in composition from the first material.

公开(公告)号：US11322414B2

公开(公告)日：2022-05-03

申请号：US16720084

申请日：2019-12-19

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Shesh Mani Pandey

IPC: H01L21/8249 ,  H01L27/06 ,  H01L29/08 ,  H01L21/74 ,  H01L29/10 ,  H01L21/265 ,  H01L21/266

Abstract: Bipolar junction transistors include a collector, a base on the collector, and an emitter on the base. The base is between the collector and the emitter. The emitter comprises first portions and a second portion on the base. The first portions of the emitter are between the second portion of the emitter and the base. The first portions and the second portion comprise doped areas that are doped with the same polarity impurity in different concentrations. The base comprises a doped area that is doped with an opposite polarity impurity from the first and second portions of the emitter. The first portions of the emitter extend from the second portion of the emitter into the base. Specifically, the second portion has a bottom surface contacting the base, and the first portions comprise at least two separate impurity regions extending from the bottom surface of the second portion into the base.

公开(公告)号：US20240282852A1

公开(公告)日：2024-08-22

申请号：US18171765

申请日：2023-02-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey ,  Kaustubh Shanbhag ,  Rajendran Krishnasamy ,  Judson R. Holt

IPC: H01L29/78 ,  H01L21/306 ,  H01L21/308 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L21/30604 ,  H01L21/308 ,  H01L29/0642 ,  H01L29/66681

Abstract: Disclosed are embodiments of a structure including a semiconductor layer and a device, which has a well region within the semiconductor layer and at least one porous region within and shallower in depth than the well region. In some embodiments, the device can be a field effect transistor (FET) (e.g., a laterally diffused metal oxide semiconductor field effect transistor (LDMOSFETs)) with a drain drift region that extends through the well region around the porous region(s) to a drain region. The porous region(s) can modify the electric field in this drain drift region, thereby improving device performance. Embodiments can vary with regard to the number, size, shape, configuration, etc. of the porous region(s) within the well region. Also disclosed herein are method embodiments for forming the semiconductor structure.

公开(公告)号：US11971572B2

公开(公告)日：2024-04-30

申请号：US17674905

申请日：2022-02-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey ,  Yusheng Bian ,  Francis O. Afzal

IPC: G02B6/036 ,  G02B6/028

CPC classification number: G02B6/0288 ,  G02B6/036

Abstract: Disclosed is an optical waveguide including a waveguide core and waveguide cladding surrounding the waveguide core. The waveguide cladding includes at least one stack of cladding material layers positioned laterally adjacent to a sidewall of the waveguide core such that each cladding material layer in the stack abuts the sidewall of the waveguide core. Each of the cladding material layers in the stack has a smaller refractive index than the waveguide core and at least two of the cladding material layers in the stack have different refractive indices, thereby tailoring field confinement and reshaping the optical mode. Different embodiments include different numbers of cladding material layers in the stack, different stacking orders of the cladding material layers, different waveguide core types, symmetric or asymmetric cladding structures on opposite sides of the waveguide core, etc. Also disclosed is a method of forming the optical waveguide.

公开(公告)号：US11967636B2

公开(公告)日：2024-04-23

申请号：US17680434

申请日：2022-02-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey ,  Hong Yu

IPC: H01L27/082 ,  H01L27/102 ,  H01L29/06 ,  H01L29/66 ,  H01L29/70 ,  H01L29/735

CPC classification number: H01L29/735 ,  H01L29/0649 ,  H01L29/6625

Abstract: Structures for a bipolar junction transistor and methods of fabricating a structure for a bipolar junction transistor. The structure includes a first terminal having a first raised semiconductor layer, a second terminal having a second raised semiconductor layer, and a base layer positioned laterally between the first raised semiconductor layer and the second raised semiconductor layer. The structure further includes a spacer positioned laterally positioned between the first raised semiconductor layer and the base layer. The spacer includes a dielectric material and an airgap surrounded by the dielectric material.