公开(公告)号：US20220254715A1

公开(公告)日：2022-08-11

申请号：US17169947

申请日：2021-02-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Steven M. Shank ,  Venkata N. R. Vanukuru

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including a device layer including a device on a substrate. A local interconnect layer is over the device layer, and includes a first dielectric material over the substrate. The first dielectric material has a first effective dielectric constant. A second dielectric material is over the device and adjacent the first dielectric material. The second dielectric material has a second effective dielectric constant less than the first effective dielectric constant.

公开(公告)号：US11574863B2

公开(公告)日：2023-02-07

申请号：US17169947

申请日：2021-02-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Steven M. Shank ,  Venkata N. R. Vanukuru

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including a device layer including a device on a substrate. A local interconnect layer is over the device layer, and includes a first dielectric material over the substrate. The first dielectric material has a first effective dielectric constant. A second dielectric material is over the device and adjacent the first dielectric material. The second dielectric material has a second effective dielectric constant less than the first effective dielectric constant.

公开(公告)号：US11651884B2

公开(公告)日：2023-05-16

申请号：US16365121

申请日：2019-03-26

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Venkata N. R. Vanukuru ,  Umesh Kumar Shukla ,  Sandeep Torgal

IPC: H01L23/52 ,  H01F17/00 ,  H01L23/60 ,  H01L23/522

CPC classification number: H01F17/0013 ,  H01L23/5227 ,  H01L23/60

Abstract: Structures that include a peaking inductor and a T-coil, and methods associated with forming such structures. A back-end-of-line interconnect structure includes a first metallization level, a second metallization level, and a third metallization level arranged between the first metallization level and the second metallization level. The T-coil includes a first inductor with a first coil arranged in the first metallization level and a second inductor with a second coil arranged in the second metallization level. A peaking inductor includes a coil arranged in the third metallization level. The first coil of the first inductor, the second coil of the second inductor, and the coil of the peaking inductor are stacked in the back-end-of-line interconnect structure with an overlapping arrangement.

公开(公告)号：US11545548B1

公开(公告)日：2023-01-03

申请号：US17361848

申请日：2021-06-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Venkata N. R. Vanukuru

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L29/06 ,  H01L27/118 ,  H01L21/762 ,  H01L27/088

Abstract: Structures for a semiconductor device including airgap isolation and methods of forming a semiconductor device structure that includes airgap isolation. The structure includes a trench isolation region, an active region of semiconductor material surrounded by the trench isolation region, and a field-effect transistor including a gate within the active region. The structure further includes a dielectric layer over the field-effect transistor, a first gate contact coupled to the gate, and a second gate contact coupled to the gate. The first and second gate contacts are positioned in the dielectric layer over the active region, and the second gate contact is spaced along a longitudinal axis of the gate from the first gate contact. The structure further includes an airgap including a portion positioned in the dielectric layer over the gate between the first and second gate contacts.

公开(公告)号：US11444160B2

公开(公告)日：2022-09-13

申请号：US17155182

申请日：2021-01-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anupam Dutta ,  Venkata N. R. Vanukuru ,  John J. Ellis-Monaghan

IPC: H01L29/10 ,  H01L21/761 ,  H01L21/762 ,  H01L29/08 ,  H01L29/861

Abstract: The disclosure provides an integrated circuit (IC) structure with a body contact to a well with multiple diode junctions. A first doped well is in a substrate. A transistor is on the first doped well. A trench isolation (TI) is adjacent a portion of the first doped well. A second doped well within the substrate has a bottom surface beneath a bottom surface of the first doped well. A sidewall of the TI horizontally abuts the second doped well. A first diode junction is between the second doped well and the first doped well. A second diode junction is between the second doped well and the substrate. A body contact is on the second doped well.

公开(公告)号：US12243923B2

公开(公告)日：2025-03-04

申请号：US17506992

申请日：2021-10-21

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Venkata N. R. Vanukuru ,  Mark Levy

IPC: H01L29/423 ,  H01L29/08 ,  H01L29/10

Abstract: Structures for a transistor including regions for landing gate contacts and methods of forming a structure for a transistor that includes regions for landing gate contacts. The structure includes a field-effect transistor having a source region, a gate region, a gate with a sidewall, and a gate extension with a section adjoined to the sidewall. The structure further includes a dielectric layer over the field-effect transistor, and a gate contact positioned in the dielectric layer to land on at least the section of the gate extension.

公开(公告)号：US11411087B2

公开(公告)日：2022-08-09

申请号：US17151343

申请日：2021-01-18

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： John J. Ellis-Monaghan ,  Anupam Dutta ,  Satyasuresh V. Choppalli ,  Venkata N. R. Vanukuru ,  Michel Abou-Khalil

IPC: H01L29/78 ,  H01L29/40

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with a high impedance semiconductor material between a substrate and transistor. The IC structure may include: a substrate, a high impedance semiconductor material on a portion of the substrate, and a transistor on a top surface of the high impedance semiconductor material. The transistor includes a semiconductor channel region horizontally between a first source/drain (S/D) region and a second S/D region. The high impedance semiconductor material is vertically between the transistor and the substrate; a first insulator region is on the substrate and horizontally adjacent the first S/D region; and a first doped well is on the substrate and horizontally adjacent the first insulator region. The first insulator region is horizontally between the first doped well and the transistor.