公开(公告)号：US11444160B2

公开(公告)日：2022-09-13

申请号：US17155182

申请日：2021-01-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anupam Dutta ,  Venkata N. R. Vanukuru ,  John J. Ellis-Monaghan

IPC: H01L29/10 ,  H01L21/761 ,  H01L21/762 ,  H01L29/08 ,  H01L29/861

Abstract: The disclosure provides an integrated circuit (IC) structure with a body contact to a well with multiple diode junctions. A first doped well is in a substrate. A transistor is on the first doped well. A trench isolation (TI) is adjacent a portion of the first doped well. A second doped well within the substrate has a bottom surface beneath a bottom surface of the first doped well. A sidewall of the TI horizontally abuts the second doped well. A first diode junction is between the second doped well and the first doped well. A second diode junction is between the second doped well and the substrate. A body contact is on the second doped well.

公开(公告)号：US12170329B2

公开(公告)日：2024-12-17

申请号：US17692218

申请日：2022-03-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anupam Dutta ,  Vvss Satyasuresh Choppalli ,  Rajendran Krishnasamy

IPC: H01L29/78 ,  H01L21/3215 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66

Abstract: According to various embodiments, there is provided a MOSFET device. The MOSFET device may include a substrate; a first doped region disposed in the substrate; a second doped region disposed in the substrate, wherein the first doped region and the second doped region are laterally adjacent to each other; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a gate disposed on the substrate, over the first and second doped regions, and between the third and fourth doped regions; and at least one high resistance region embedded in at least the second doped region, wherein the first doped region has a first conductivity type, wherein the second doped region, the third doped region, and the fourth doped region have a second conductivity type, wherein the first conductivity type and the second conductivity type are different.

公开(公告)号：US20240266422A1

公开(公告)日：2024-08-08

申请号：US18166041

申请日：2023-02-08

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anupam Dutta ,  Satyasuresh Vvss Choppalli ,  Rajendran Krishnasamy ,  Robert J. Gauthier, JR. ,  Anindya Nath

IPC: H01L29/745

CPC classification number: H01L29/7455

Abstract: Disclosed structures include a semiconductor controlled rectifier or bi-directional semiconductor controlled rectifier with a trigger voltage (Vtrig) that is tunable. Some structures include a semiconductor controlled rectifier with an Nwell and Pwell in a semiconductor layer, with a P-type diffusion region in the Nwell, and with an N-type diffusion region in the Pwell. Gate(s) on the well(s) are separated from the junction between the wells and from the diffusion regions. Other structures include a bidirectional semiconductor controlled rectifier with a Pwell between first and second Nwells in a semiconductor layer, with first P-type and N-type diffusion regions in the first Nwell, and with second P-type and N-type diffusion regions in the second Nwell. Gate(s) on the well(s) are separated from junctions between the Nwells and the Pwell and from any diffusion regions. In these structures, the gate(s) can be left floating or biased to tune Vtrig using gate leakage current.

公开(公告)号：US11804491B2

公开(公告)日：2023-10-31

申请号：US17872812

申请日：2022-07-25

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anupam Dutta

IPC: H01L27/12 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L27/1203 ,  H01L29/41733 ,  H01L29/42384

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with staggered body contacts and methods of manufacture. The device includes: a gate structure on a semiconductor substrate material, the gate structure comprising a gate body with a width and a length; a plurality of body contacts electrically contacting a channel region under the gate body on at least one side of the gate body along its width; and isolation structures isolating the plurality of body contacts from a source region and a drain region associated with the gate structure.

公开(公告)号：US12211929B1

公开(公告)日：2025-01-28

申请号：US18663523

申请日：2024-05-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Alexander Derrickson ,  Anupam Dutta ,  John Pekarik ,  Vibhor Jain ,  V V S S Satyasuresh Choppalli ,  Rui Tze Toh ,  Oscar Restrepo

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. The structure comprises an intrinsic base including a first semiconductor layer, a collector including a second semiconductor layer, and an emitter including a third semiconductor layer. The first semiconductor layer, which comprises silicon-germanium, includes a first portion and a second portion adjacent to the first portion. The second semiconductor layer includes a portion on the first portion of the first semiconductor layer, and the third semiconductor layer includes a portion on the second portion of the first semiconductor layer. The structure further comprises a dielectric spacer laterally between the portion of the second semiconductor layer and the portion of the third semiconductor layer.

公开(公告)号：US11411087B2

公开(公告)日：2022-08-09

申请号：US17151343

申请日：2021-01-18

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： John J. Ellis-Monaghan ,  Anupam Dutta ,  Satyasuresh V. Choppalli ,  Venkata N. R. Vanukuru ,  Michel Abou-Khalil

IPC: H01L29/78 ,  H01L29/40

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with a high impedance semiconductor material between a substrate and transistor. The IC structure may include: a substrate, a high impedance semiconductor material on a portion of the substrate, and a transistor on a top surface of the high impedance semiconductor material. The transistor includes a semiconductor channel region horizontally between a first source/drain (S/D) region and a second S/D region. The high impedance semiconductor material is vertically between the transistor and the substrate; a first insulator region is on the substrate and horizontally adjacent the first S/D region; and a first doped well is on the substrate and horizontally adjacent the first insulator region. The first insulator region is horizontally between the first doped well and the transistor.

公开(公告)号：US20220190116A1

公开(公告)日：2022-06-16

申请号：US17155182

申请日：2021-01-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anupam Dutta ,  Venkata N.R. Vanukuru ,  John J. Ellis-Monaghan

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/861 ,  H01L21/762 ,  H01L21/761

Abstract: The disclosure provides an integrated circuit (IC) structure with a body contact to a well with multiple diode junctions. A first doped well is in a substrate. A transistor is on the first doped well. A trench isolation (TI) is adjacent a portion of the first doped well. A second doped well within the substrate has a bottom surface beneath a bottom surface of the first doped well. A sidewall of the TI horizontally abuts the second doped well. A first diode junction is between the second doped well and the first doped well. A second diode junction is between the second doped well and the substrate. A body contact is on the second doped well.

公开(公告)号：US12191300B2

公开(公告)日：2025-01-07

申请号：US17662921

申请日：2022-05-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Robert J. Gauthier, Jr. ,  Rajendran Krishnasamy ,  Anupam Dutta ,  Anindya Nath ,  Xiangxiang Lu ,  Satyasuresh Vvss Choppalli ,  Lin Lin

IPC: H01L27/02

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with resistive semiconductor material for a back well. The IC structure may include a semiconductor substrate having a deep well, and a device within a first portion of the deep well. The device includes a first doped semiconductor material coupled to a first contact, and a second doped semiconductor material coupled to a second contact. The deep well couples the first doped semiconductor material to the second doped semiconductor material. A first back well is within a second portion of the deep well. A first resistive semiconductor material is within the deep well and defines a boundary between the first portion of the deep well and the second portion of the deep well.

公开(公告)号：US20240429208A1

公开(公告)日：2024-12-26

申请号：US18340230

申请日：2023-06-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anupam Dutta ,  Satyasuresh Vvss Choppalli ,  Rui Tze Toh ,  Mei Hui June Goh

IPC: H01L25/07 ,  H01L23/00 ,  H01L25/00

Abstract: Disclosed structures and methods include a top chip flipped relative to a bottom chip and bonded thereto. On the top chip, dielectric material layers separate a transistor from the bottom chip. The transistor includes source and drain regions, a body region on a channel region between the source and drain regions, and a gate structure adjacent to and between the channel region and the dielectric material layers. An insulator layer is on the transistor opposite the dielectric material layers and includes an opening extending to the body region. Optionally, a semiconductor layer is at the bottom of the opening. A contact extends into the opening to the body region (or to the semiconductor layer thereon, if applicable).

公开(公告)号：US11476279B2

公开(公告)日：2022-10-18

申请号：US16987170

申请日：2020-08-06

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Anupam Dutta

IPC: H01L27/12 ,  H01L29/417 ,  H01L29/423

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with staggered body contacts and methods of manufacture. The device includes: a gate structure on a semiconductor substrate material, the gate structure comprising a gate body with a width and a length; a plurality of body contacts electrically contacting a channel region under the gate body on at least one side of the gate body along its width; and isolation structures isolating the plurality of body contacts from a source region and a drain region associated with the gate structure.