公开(公告)号：US12027580B2

公开(公告)日：2024-07-02

申请号：US17028178

申请日：2020-09-22

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Anthony K. Stamper ,  Siva P. Adusumilli ,  Bruce W. Porth ,  John J. Ellis-Monaghan

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/762 ,  H01L21/764

CPC classification number: H01L29/0649 ,  H01L21/02505 ,  H01L21/7624 ,  H01L21/764

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a semiconductor on insulator substrate with cavity structures and methods of manufacture. The structure includes: a bulk substrate with at least one rectilinear cavity structure; an insulator material sealing the at least one rectilinear cavity structure; and a buried insulator layer on the bulk substrate and over the at least one rectilinear cavity structure.

公开(公告)号：US20240063315A1

公开(公告)日：2024-02-22

申请号：US17820979

申请日：2022-08-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva P. Adusumilli ,  Ramsey Hazbun ,  John J. Ellis-Monaghan ,  Rajendran Krishnasamy

IPC: H01L31/0232 ,  H01L31/028 ,  H01L31/105 ,  H01L31/18

CPC classification number: H01L31/02327 ,  H01L31/028 ,  H01L31/105 ,  H01L31/1808

Abstract: A photodetector structure includes a first semiconductor material layer over a doped well in a substrate. The photodetector structure includes an air gap vertically between the first semiconductor material layer and a first portion of the doped well. The photodetector structure includes an insulative collar on the first portion of the doped well and laterally surrounding the air gap. The photodetector structure may include a second semiconductor material layer on the first portion of the doped well and laterally surrounded by the insulative collar. The photodetector structure may include a third semiconductor layer over the first semiconductor layer.

公开(公告)号：US20230417695A1

公开(公告)日：2023-12-28

申请号：US17808176

申请日：2022-06-22

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva P. Adusumilli ,  Mark D. Levy ,  Ramsey M. Hazbun ,  John J. Ellis-Monaghan

IPC: G01N27/06 ,  H01L31/105 ,  H01L31/0352 ,  H01L31/18

CPC classification number: G01N27/06 ,  H01L31/105 ,  H01L31/035209 ,  H01L31/1804

Abstract: Disclosed is a semiconductor structure with a photodiode including: a well region with a first-type conductivity in a substrate, a trench in the well region, and multiple conformal semiconductor layers in the trench. The semiconductor layers include a first semiconductor layer, which is, for example, an intrinsic semiconductor layer and lines the trench, and a second semiconductor layer, which has a second-type conductivity and which is on the first semiconductor layer within (but not filling) the trench and which also extends outside the trench onto a dielectric layer. An additional dielectric layer extends over and caps a cavity that is at least partially within the trench such that surfaces of the second semiconductor layer are exposed within the cavity. Fluid inlet/outlet ports extend to the cavity and contacts extend to the well region and to the second semiconductor layer. Also disclosed are methods for forming and using the semiconductor structure.

公开(公告)号：US11488980B2

公开(公告)日：2022-11-01

申请号：US17003179

申请日：2020-08-26

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Siva P. Adusumilli ,  Anthony K. Stamper ,  Bruce W. Porth ,  John J. Ellis-Monaghan

IPC: H01L27/12 ,  H01L21/762 ,  H01L29/06

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a wafer with localized cavity structures and methods of manufacture. A structure includes a bulk substrate with localized semiconductor on insulator (SOI) regions and bulk device regions, the localized SOI regions includes multiple cavity structures and substrate material of the bulk substrate.

公开(公告)号：US11411087B2

公开(公告)日：2022-08-09

申请号：US17151343

申请日：2021-01-18

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： John J. Ellis-Monaghan ,  Anupam Dutta ,  Satyasuresh V. Choppalli ,  Venkata N. R. Vanukuru ,  Michel Abou-Khalil

IPC: H01L29/78 ,  H01L29/40

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with a high impedance semiconductor material between a substrate and transistor. The IC structure may include: a substrate, a high impedance semiconductor material on a portion of the substrate, and a transistor on a top surface of the high impedance semiconductor material. The transistor includes a semiconductor channel region horizontally between a first source/drain (S/D) region and a second S/D region. The high impedance semiconductor material is vertically between the transistor and the substrate; a first insulator region is on the substrate and horizontally adjacent the first S/D region; and a first doped well is on the substrate and horizontally adjacent the first insulator region. The first insulator region is horizontally between the first doped well and the transistor.

公开(公告)号：US11410872B2

公开(公告)日：2022-08-09

申请号：US16206375

申请日：2018-11-30

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Siva P. Adusumilli ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  Anthony K. Stamper

IPC: H01L29/00 ,  H01L29/51 ,  H01L21/762 ,  H01L21/308 ,  H01L29/10 ,  H01L21/306 ,  H01L29/06

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to oxidized cavity structures within and under semiconductor devices and methods of manufacture. The structure includes: a substrate material; active devices over the substrate material; an oxidized trench structure extending into the substrate and surrounding the active devices; and one or more oxidized cavity structures extending from the oxidized trench structure and formed in the substrate material under the active devices.

公开(公告)号：US20220190116A1

公开(公告)日：2022-06-16

申请号：US17155182

申请日：2021-01-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anupam Dutta ,  Venkata N.R. Vanukuru ,  John J. Ellis-Monaghan

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/861 ,  H01L21/762 ,  H01L21/761

Abstract: The disclosure provides an integrated circuit (IC) structure with a body contact to a well with multiple diode junctions. A first doped well is in a substrate. A transistor is on the first doped well. A trench isolation (TI) is adjacent a portion of the first doped well. A second doped well within the substrate has a bottom surface beneath a bottom surface of the first doped well. A sidewall of the TI horizontally abuts the second doped well. A first diode junction is between the second doped well and the first doped well. A second diode junction is between the second doped well and the substrate. A body contact is on the second doped well.

公开(公告)号：US20220165676A1

公开(公告)日：2022-05-26

申请号：US16953441

申请日：2020-11-20

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Vibhor Jain ,  Sunil K. Singh ,  Johnatan A. Kantarovsky ,  Siva P. Adusumilli ,  Sebastian T. Ventrone ,  John J. Ellis-Monaghan ,  Yves T. Ngu

IPC: H01L23/544 ,  H01L23/00

Abstract: The disclosure provides a method to authenticate an integrated circuit (IC) structure. The method may include forming a first authentication film (AF) material within the IC structure. A composition of the first AF material is different from an adjacent material within the IC structure. The method includes converting the first AF material into a void within the IC structure. Additionally, the method includes creating an authentication map of the IC structure to include a location of the void in the IC structure for authentication of the IC structure.

公开(公告)号：US11316045B2

公开(公告)日：2022-04-26

申请号：US16691691

申请日：2019-11-22

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Anthony K. Stamper ,  Aaron L. Vallett ,  Steven M. Shank ,  John J. Ellis-Monaghan

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66 ,  H01L29/417 ,  H01L29/49 ,  H01L29/51

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical field effect transistors (FETS) and methods of manufacture. The structure includes: a substrate material; at least one vertically oriented gate structure extending into the substrate material and composed of a gate dielectric material and conductive gate material; and vertically oriented source/drain regions extending into the substrate material and composed of conductive dopant material and a silicide on the source/drain regions.

公开(公告)号：US20210336005A1

公开(公告)日：2021-10-28

申请号：US16855236

申请日：2020-04-22

Applicant: GLOBALFOUNDRIES U.S. Inc

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Vibhor Jain ,  John J. Ellis-Monaghan

IPC: H01L29/08 ,  H01L29/78

Abstract: The disclosure provides a field effect transistor (FET) stack with methods to form the same. The FET stack includes a first transistor over a substrate. The first transistor includes a first active semiconductor material including a first channel region between a first set of source/drain terminals, and a first gate structure over the first channel region. The first gate structure includes a first gate insulator of a first thickness above the first channel region. A second transistor is over the substrate and horizontally separated from the first transistor. A second gate structure of the second transistor may include a second gate insulator of a second thickness above a second channel region, the second thickness being greater than the first thickness. A shared gate node may be coupled to each of the first gate structure and the second gate structure.