公开(公告)号：US11121087B2

公开(公告)日：2021-09-14

申请号：US16726447

申请日：2019-12-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Nicholas LiCausi ,  Julien Frougier ,  Keith Donegan ,  Hyung Woo Kim

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528 ,  G11C5/06

Abstract: One illustrative device disclosed herein includes a layer of insulating material having an upper surface positioned at a first level and a recessed conductive interconnect structure positioned at least partially within the layer of insulating material, wherein the recessed conductive interconnect structure has a recessed upper surface that is positioned at a second level that is below the first level. In this example, the device also includes a recess defined in the recessed conductive interconnect structure, a memory cell positioned above the recessed conductive interconnect structure and a conductive via plug that is conductively coupled to the recessed conductive interconnect structure and a lower conductive material of the memory cell, wherein at least a portion of the conductive via plug is positioned in the recess defined in the recessed conductive interconnect.

公开(公告)号：US20210240445A1

公开(公告)日：2021-08-05

申请号：US16776909

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hemant M. Dixit ,  Julien Frougier ,  Bipul C. Paul ,  William J. Taylor, JR.

IPC: G06F7/58 ,  G11C11/16

Abstract: Embodiments of the disclosure provide a system for providing a true random number (TRN) or physically unclonable function (PUF), including: an array of voltage controlled magnetic anisotropy (VCMA) cells; a voltage pulse tuning circuit for generating and applying a stochastically tuned voltage pulse to the VCMA cells in the array of VCMA cells, wherein the stochastically tuned voltage pulse has a magnitude and duration that provides a 50%-50% switching distribution of the VCMA cells in the array of VCMA cells; and a bit output system for reading a state of each of the VCMA cells in the array of VCMA cells to provide a TRN or PUF.

公开(公告)号：US11049934B2

公开(公告)日：2021-06-29

申请号：US16574763

申请日：2019-09-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ali Razavieh ,  Julien Frougier ,  Bradley Morgenfeld

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L29/786 ,  H01L21/321 ,  H01L21/3105

Abstract: One illustrative transistor device disclosed herein includes a nanowire matrix comprising a plurality of nanowire structures that are arranged in at least one substantially horizontally oriented row and at least two substantially vertically oriented columns, the at least two substantially vertically oriented columns being laterally spaced apart from one another in a gate width direction of the transistor device, each of the plurality of nanowire structures comprising an outer perimeter. This illustrative embodiment of the transistor device further includes a gate structure that is positioned around the outer perimeter of all of the nanowire structures in the matrix, and a gate cap positioned above the gate structure.

公开(公告)号：US20210118993A1

公开(公告)日：2021-04-22

申请号：US16655429

申请日：2019-10-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Baofu Zhu ,  Frank W. Mont ,  Julien Frougier ,  Ali Razavieh

IPC: H01L29/08 ,  H01L29/78

Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall epitaxial cavities formed in the semiconductor substrate on opposite sides of the gate structure. In one embodiment, each of the first and second overall epitaxial cavities includes a substantially vertically oriented upper epitaxial cavity and a lower epitaxial cavity, wherein the substantially vertically oriented upper epitaxial cavity extends from an upper surface of the semiconductor substrate to the lower epitaxial cavity. A lateral width of the lower epitaxial cavity is greater than a lateral width of the upper epitaxial cavity. The device also includes epitaxial semiconductor material positioned in each of the first and second overall epitaxial cavities.

公开(公告)号：US10903317B1

公开(公告)日：2021-01-26

申请号：US16534317

申请日：2019-08-07

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Julien Frougier ,  Ruilong Xie ,  Kangguo Cheng ,  Chanro Park

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

Abstract: A gate-all-around field effect transistor (GAAFET) and method. The GAAFET includes nanosheets, a gate around center portions of the nanosheets, and inner spacers aligned below end portions. The nanosheet end portions are tapered from the source/drain regions to the gate and the inner spacers are tapered from the gate to the source/drain regions. Each inner spacer includes: a first spacer layer, which has a uniform thickness and extends laterally from the gate to an adjacent source/drain region; a second spacer layer, which fills the space between a planar top surface of the first spacer layer and a tapered end portion of the nanosheet above; and, for all but the lowermost inner spacers, a third spacer layer, which is the same material as the second spacer layer and which fills the space between a planar bottom surface of the first spacer layer and a tapered end portion of the nanosheet below.

公开(公告)号：US11435982B2

公开(公告)日：2022-09-06

申请号：US16776909

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hemant M. Dixit ,  Julien Frougier ,  Bipul C. Paul ,  William J. Taylor, Jr.

IPC: G06F7/58 ,  G11C11/16

Abstract: Embodiments of the disclosure provide a system for providing a true random number (TRN) or physically unclonable function (PUF), including: an array of voltage controlled magnetic anisotropy (VCMA) cells; a voltage pulse tuning circuit for generating and applying a stochastically tuned voltage pulse to the VCMA cells in the array of VCMA cells, wherein the stochastically tuned voltage pulse has a magnitude and duration that provides a 50%-50% switching distribution of the VCMA cells in the array of VCMA cells; and a bit output system for reading a state of each of the VCMA cells in the array of VCMA cells to provide a TRN or PUF.

公开(公告)号：US11362177B2

公开(公告)日：2022-06-14

申请号：US16774157

申请日：2020-01-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Baofu Zhu ,  Frank W. Mont ,  Ali Razavieh ,  Julien Frougier

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/78

Abstract: One illustrative transistor of a first dopant type disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall epitaxial cavities formed in the semiconductor substrate on opposite sides of the gate structure. The device also includes a counter-doped epitaxial semiconductor material positioned proximate a bottom of each of the first and second overall epitaxial cavities, wherein the counter-doped epitaxial semiconductor material is doped with a second dopant type that is opposite to the first dopant type, and a same-doped epitaxial semiconductor material positioned in each of the first and second overall epitaxial cavities above the counter-doped epitaxial semiconductor material, wherein the same-doped epitaxial semiconductor material is doped with a dopant of the first dopant type.

公开(公告)号：US11205699B2

公开(公告)日：2021-12-21

申请号：US16655429

申请日：2019-10-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Arkadiusz Malinowski ,  Baofu Zhu ,  Frank W. Mont ,  Julien Frougier ,  Ali Razavieh

IPC: H01L29/08 ,  H01L29/78

Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall epitaxial cavities formed in the semiconductor substrate on opposite sides of the gate structure. In one embodiment, each of the first and second overall epitaxial cavities includes a substantially vertically oriented upper epitaxial cavity and a lower epitaxial cavity, wherein the substantially vertically oriented upper epitaxial cavity extends from an upper surface of the semiconductor substrate to the lower epitaxial cavity. A lateral width of the lower epitaxial cavity is greater than a lateral width of the upper epitaxial cavity. The device also includes epitaxial semiconductor material positioned in each of the first and second overall epitaxial cavities.

公开(公告)号：US11069819B2

公开(公告)日：2021-07-20

申请号：US16668763

申请日：2019-10-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Julien Frougier

IPC: H01L29/778 ,  H01L29/786 ,  H01L29/06 ,  H01L29/24 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423 ,  H01L29/10 ,  H01L21/8234

Abstract: Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A gate electrode has a section that is wrapped about a first side surface and a second side surface of a mandrel that is composed of a dielectric material. A channel layer has a channel region that is positioned in part between the first side surface of the mandrel and the section of the gate electrode. The channel layer is composed of a two-dimensional material.

公开(公告)号：US20210193584A1

公开(公告)日：2021-06-24

申请号：US16726447

申请日：2019-12-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Nicholas LiCausi ,  Julien Frougier ,  Keith Donegan ,  Hyung Woo Kim

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  G11C5/06 ,  H01L21/768

Abstract: One illustrative device disclosed herein includes a layer of insulating material having an upper surface positioned at a first level and a recessed conductive interconnect structure positioned at least partially within the layer of insulating material, wherein the recessed conductive interconnect structure has a recessed upper surface that is positioned at a second level that is below the first level. In this example, the device also includes a recess defined in the recessed conductive interconnect structure, a memory cell positioned above the recessed conductive interconnect structure and a conductive via plug that is conductively coupled to the recessed conductive interconnect structure and a lower conductive material of the memory cell, wherein at least a portion of the conductive via plug is positioned in the recess defined in the recessed conductive interconnect.