公开(公告)号：US20240006524A1

公开(公告)日：2024-01-04

申请号：US17852873

申请日：2022-06-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Mark D. LEVY ,  Qizhi LIU ,  Jeonghyun HWANG

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/66462

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a patterned buried porous layer of semiconductor material and a device over the patterned buried porous layer, and methods of manufacture. The structure includes: a semiconductor substrate includes a patterned buried porous layer within the semiconductor substrate; a semiconductor compound material over the semiconductor substrate and the patterned buried porous layer; and at least one device on the semiconductor compound material. The non-patterned portions of the semiconductor substrate provide a thermal pathway within the semiconductor substrate.

公开(公告)号：US20240006491A1

公开(公告)日：2024-01-04

申请号：US17852966

申请日：2022-06-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Uppili S. RAGHUNATHAN ,  Vibhor JAIN ,  Qizhi LIU ,  Yves T. NGU ,  Ajay RAMAN ,  Rajendran KRISHNASAMY ,  Alvin J. JOSEPH

IPC: H01L29/10 ,  H01L29/08

CPC classification number: H01L29/1095 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with a stepped emitter and methods of manufacture. The structure includes: a collector; a base over the collector; and an emitter over the base, the emitter comprising at least one stepped feature over the base.

公开(公告)号：US20210091214A1

公开(公告)日：2021-03-25

申请号：US16909376

申请日：2020-06-23

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Herbert HO ,  Vibhor JAIN ,  John J. PEKARIK ,  Claude ORTOLLAND ,  Judson R. HOLT ,  Qizhi LIU ,  Viorel ONTALUS

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a device with a marker layer and methods of manufacture. The device includes: a collector region; an intrinsic base region above the collector region; an emitter region comprising emitter material and a marker layer vertically between the intrinsic base region and the emitter material; and an extrinsic base region in electrical contact with the intrinsic base region.

公开(公告)号：US20210091195A1

公开(公告)日：2021-03-25

申请号：US16732755

申请日：2020-01-02

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Judson R. HOLT ,  Vibhor JAIN ,  Qizhi LIU ,  Ramsey HAZBUN ,  Pernell DONGMO ,  John J. PEKARIK ,  Cameron E. LUCE

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/737 ,  H01L29/08

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a sub-collector region in a substrate; a collector region above the sub-collector region, the collector region composed of semiconductor material; an intrinsic base region composed of intrinsic base material surrounded by the semiconductor material above the collector region; and an emitter region above the intrinsic base region.