公开(公告)号：US11195761B2

公开(公告)日：2021-12-07

申请号：US16804920

申请日：2020-02-28

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Haiting Wang ,  Hong Yu ,  Steven J. Bentley

IPC: H01L27/092 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L23/535

Abstract: An integrated circuit (IC) structure includes a long channel (LC) gate structure over a long channel region, the LC gate structure having a first gate height; and a short channel (SC) gate structure over a short channel region, the SC gate structure having a second gate height. The short channel region is shorter in length than the long channel region. The second gate height of the SC gate structure is no larger than the first gate height of the LC gate structure.

公开(公告)号：US20210272851A1

公开(公告)日：2021-09-02

申请号：US16804920

申请日：2020-02-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Haiting Wang ,  Hong Yu ,  Steven J. Bentley

IPC: H01L21/8234 ,  H01L27/088 ,  H01L23/535 ,  H01L29/423

Abstract: An integrated circuit (IC) structure includes a long channel (LC) gate structure over a long channel region, the LC gate structure having a first gate height; and a short channel (SC) gate structure over a short channel region, the SC gate structure having a second gate height. The short channel region is shorter in length than the long channel region. The second gate height of the SC gate structure is no larger than the first gate height of the LC gate structure.

公开(公告)号：US20250089284A1

公开(公告)日：2025-03-13

申请号：US18243910

申请日：2023-09-08

Applicant: GlobalFoundries U.S. Inc.

Inventor： Johnatan Avraham Kantarovsky ,  Michael J. Zierak ,  Santosh Sharma ,  Mark D. Levy ,  Steven J. Bentley

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/40 ,  H01L29/417 ,  H01L29/778

Abstract: A structure according to the disclosure includes a dielectric layer over a substrate and horizontally between a gate terminal and a source/drain (S/D) terminal. The dielectric layer has a first surface proximal to the substrate and a second surface opposite the first surface. The dielectric layer has a plurality of recesses in the second surface. At least some of the plurality of recesses have different depths. A conductive field plate includes a metal layer on the second surface and within the plurality of recesses. The conductive field plate is electrically isolated from the gate terminal and the S/D terminal.

公开(公告)号：US20240085247A1

公开(公告)日：2024-03-14

申请号：US17931670

申请日：2022-09-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Santosh Sharma ,  Michael J. Zierak ,  Steven J. Bentley ,  Johnatan Avraham Kantarovsky

IPC: G01K7/18 ,  H01C7/04 ,  H01L27/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/778

CPC classification number: G01K7/183 ,  H01C7/041 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/7786

Abstract: A structure includes a negative temperature coefficient (NTC) resistor for use in gallium nitride (GaN) technology. The NTC resistor includes a p-type doped GaN (pGaN) layer, and a gallium nitride (GaN) heterojunction structure under the pGaN layer. The GaN heterojunction structure includes a barrier layer and a channel layer. An isolation region extends across an interface of the barrier layer and the channel layer, and a first metal electrode is on the pGaN layer spaced from a second metal electrode on the pGaN layer. The NTC resistor can be used as a temperature compensated reference in a structure providing a temperature detection circuit. The temperature detection circuit includes an enhancement mode HEMT sharing parts with the NTC resistor and includes temperature independent current sources including depletion mode HEMTs.

公开(公告)号：US20240105595A1

公开(公告)日：2024-03-28

申请号：US17934389

申请日：2022-09-22

Applicant: GlobalFoundries U.S. Inc.

Inventor： Johnatan A. Kantarovsky ,  Santosh Sharma ,  Michael J. Zierak ,  Steven J. Bentley ,  Ephrem G. Gebreselasie

IPC: H01L23/525 ,  H01L21/76 ,  H01L27/06 ,  H01L29/20

CPC classification number: H01L23/5256 ,  H01L21/7605 ,  H01L27/0605 ,  H01L29/2003

Abstract: Embodiments of the disclosure provide an electrically programmable fuse (efuse) over crystalline semiconductor material. A structure according to the disclosure includes a plurality of crystalline semiconductor layers. Each crystalline semiconductor layer includes a compound material. A metallic layer is on the plurality of crystalline semiconductor layers. The metallic layer has a lower resistivity than an uppermost layer of the plurality of crystalline semiconductor layers. A pair of gate conductors is on respective portions of the metallic layer. The metallic layer defines an electrically programmable fuse (efuse) link between the gate conductors.

公开(公告)号：US12183814B1

公开(公告)日：2024-12-31

申请号：US18615615

申请日：2024-03-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： Steven J. Bentley ,  Francois Hebert ,  Lawrence Selvaraj Susai ,  Johnatan A Kantarovsky ,  Michael Zierak ,  Mark D. Levy ,  John Ellis-Monaghan

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to multi-channel transistors and methods of manufacture. The structure includes: a gate structure; a single channel layer in a channel region under the gate structure; a drift region adjacent to the gate structure; and multiple channel layers in the drift region coupled to the single channel layer under the gate structure.

公开(公告)号：US20240063219A1

公开(公告)日：2024-02-22

申请号：US17819980

申请日：2022-08-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Santosh Sharma ,  Jerry Joseph James ,  Steven J. Bentley ,  Francois Hebert ,  Richard J. Rassel

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/778 ,  H01L29/40 ,  H01L29/06

CPC classification number: H01L27/0883 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/401 ,  H01L29/402 ,  H01L29/0607

Abstract: A structure for an III-V integrated circuit includes an integrated depletion and enhancement mode gallium nitride high electron mobility transistors (HEMTs). The structure includes a first, depletion mode HEMT having a first source, a first drain and a first fieldplate gate between the first source and the first drain, and a second, enhancement mode HEMT having a second source and a second drain. The second HEMT also includes a gallium nitride (GaN) gate and a second fieldplate gate between the second source and the second drain. The second fieldplate gate of the second HEMT may be closer to the second drain than the GaN gate. The structure provides a reliable, low leakage, high voltage depletion mode HEMT (e.g., with operating voltages of greater than 100V, but with a pinch-off voltage of less than 6 Volts) integrated with a gallium nitride (GaN) gate-based enhancement mode HEMT.