公开(公告)号：US11935928B2

公开(公告)日：2024-03-19

申请号：US17747476

申请日：2022-05-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hong Yu ,  Jianwei Peng ,  Vibhor Jain

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/737

CPC classification number: H01L29/41708 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/42304 ,  H01L29/66242 ,  H01L29/7371

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with self-aligned asymmetric spacer and methods of manufacture. The structure includes: a base formed on a semiconductor substrate; an asymmetrical spacer surrounding the base; an emitter on a first side of the base and separated from the base by the asymmetrical spacer; and a collector on a second side of the base and separated from the base by the asymmetrical spacer.

公开(公告)号：US11923417B2

公开(公告)日：2024-03-05

申请号：US17692517

申请日：2022-03-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hong Yu ,  Shesh Mani Pandey

IPC: H01L29/10 ,  H01L21/8222 ,  H01L27/082 ,  H01L29/66 ,  H01L29/735 ,  H01L29/737

CPC classification number: H01L29/1008 ,  H01L29/6625 ,  H01L29/735 ,  H01L21/8222 ,  H01L27/082 ,  H01L29/737

Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a substrate having a well, a first terminal including a first raised semiconductor layer, a second terminal including a second raised semiconductor layer, and a base layer positioned in a lateral direction between the first raised semiconductor layer of the first terminal and the second raised semiconductor layer of the second terminal. The base layer has an overlapping arrangement with the well. The structure further includes a dielectric layer positioned in a vertical direction between the first terminal and the substrate, the second terminal and the substrate, and the base layer and the substrate.

公开(公告)号：US11769806B2

公开(公告)日：2023-09-26

申请号：US17525236

申请日：2021-11-12

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hong Yu ,  Jagar Singh

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/40 ,  H01L29/737 ,  H01L29/735

CPC classification number: H01L29/41708 ,  H01L29/401 ,  H01L29/66242 ,  H01L29/735 ,  H01L29/737

Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a first terminal having a first raised semiconductor layer having a top surface and a side surface, a second terminal having a second raised semiconductor layer, and a base layer positioned in a lateral direction between the first raised semiconductor layer of the first terminal and the second raised semiconductor layer of the second terminal. The structure further includes a contact positioned to overlap with the top surface and the side surface of the first raised semiconductor layer.

公开(公告)号：US20230223462A1

公开(公告)日：2023-07-13

申请号：US17657154

申请日：2022-03-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hong Yu ,  Alexander M. Derrickson ,  Judson R. Holt

IPC: H01L29/73 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/73 ,  H01L29/66234 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1095 ,  H01L29/0653

Abstract: Embodiments of the disclosure provide a bipolar transistor structure including a semiconductor fin on a substrate. The semiconductor fin has a first doping type, a length in a first direction, and a width in a second direction perpendicular to the first direction. A first emitter/collector (E/C) material is adjacent a first sidewall of the semiconductor fin along the width of the semiconductor fin. The first E/C material has a second doping type opposite the first doping type. A second E/C material is adjacent a second sidewall of the semiconductor fin along the width of the semiconductor fin. The second E/C material has the second doping type. A width of the first E/C material is different from a width of the second E/C material.

公开(公告)号：US11205648B2

公开(公告)日：2021-12-21

申请号：US16866663

申请日：2020-05-05

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anton V. Tokranov ,  James P. Mazza ,  Elizabeth A. Strehlow ,  Harold Mendoza ,  Jay A. Mody ,  Clynn J. Mathew ,  Hong Yu ,  Yea-Sen Lin

IPC: H01L27/088 ,  H01L29/36 ,  H01L29/78 ,  H01L27/06 ,  H01L29/66 ,  H01L21/8234

Abstract: An integrated circuit (IC) structure with a single active region having a doping profile different than that of a set of active regions, is disclosed. The IC structure provides a single active region, e.g., a fin, on a substrate with a first doping profile, and a set of active regions, e.g., fins, electrically isolated from the single active region on the substrate. The set of active regions have a second doping profile that is different than the first doping profile of the single active region. For example, the second doping profile can have a deeper penetration into the substrate than the first doping profile.

公开(公告)号：US20210367060A1

公开(公告)日：2021-11-25

申请号：US17398479

申请日：2021-08-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Haiting Wang ,  Hong Yu ,  Zhenyu Hu

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L29/45 ,  H01L21/285 ,  H01L29/417

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to single fin structures and methods of manufacture. The structure includes: an active single fin structure; a plurality of dummy fin structures on opposing sides of the active single fin structure; source and drain regions formed on the active single fin structure and the dummy fin structures; recessed shallow trench isolation (STI) regions between the dummy fin structures and the active single fin structure and below a surface of the dummy fin structures; and contacts formed on the source and drain regions of the active single fin structure with a spacing of at least two dummy fin structures on opposing sides of the contacts.

公开(公告)号：US11037821B2

公开(公告)日：2021-06-15

申请号：US16400481

申请日：2019-05-01

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Xiaoming Yang ,  Haiting Wang ,  Hong Yu ,  Jeffrey Chee ,  Guoliang Zhu

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L21/033 ,  H01L21/32 ,  H01L21/311

Abstract: Methods of forming interconnects and structures for interconnects. A hardmask layer is patterned to form a plurality of first trenches arranged with a first pattern, and sidewall spacers are formed inside the first trenches on respective sidewalls of the hardmask layer bordering the first trenches. An etch mask is formed over the hardmask layer. The etch mask includes an opening exposing a portion of the hardmask layer between a pair of the sidewall spacers. The portion of the hardmask layer exposed by the opening in the etch mask is removed to define a second trench in the hardmask layer.

公开(公告)号：US20210151443A1

公开(公告)日：2021-05-20

申请号：US16689330

申请日：2019-11-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Meixiong Zhao ,  Randy W. Mann ,  Sanjay Parihar ,  Anton Tokranov ,  Hong Yu ,  Hongliang Shen ,  Guoxiang Ning

IPC: H01L27/11 ,  H01L21/8239 ,  H01L21/8238

Abstract: Structures including static random access memory bit cells and methods of forming a structure including static random access memory bit cells. A first bit cell includes a first plurality of semiconductor fins, and a second bit cell includes a second plurality of semiconductor fins. A deep trench isolation region is laterally positioned between the first plurality of semiconductor fins of the first bit cell and the second plurality of semiconductor fins of the second bit cell.

公开(公告)号：US20250031439A1

公开(公告)日：2025-01-23

申请号：US18354114

申请日：2023-07-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hong Yu ,  Navneet K. Jain ,  David Charles Pritchard ,  Romain H.A. Feuillette

IPC: H01L27/088 ,  H01L21/28 ,  H01L21/8234

Abstract: A disclosed structure includes a semiconductor fin on a substrate and an isolation region on the substrate laterally surrounding a lower portion of the fin. A fin-type field effect transistor (FINFET) includes an upper portion of the fin and an isolation structure, and a gate structure are on the isolation region and positioned laterally adjacent to the upper portion of the fin. The gate structure also extends over the top of the fin and abuts the isolation structure. The FINFET also includes an independently biasable supplementary gate structure integrated into the isolation structure. Specifically, an opening extends into the isolation structure adjacent to, but separated from, the fin. The supplementary gate structure includes a conductor layer within the opening and that portion of the isolation structure between the conductor layer and the semiconductor fin. Also disclosed are associated methods.

公开(公告)号：US12107154B2

公开(公告)日：2024-10-01

申请号：US18324489

申请日：2023-05-26

Applicant: GlobalFoundries U.S. Inc.

Inventor： Haiting Wang ,  Hong Yu ,  Zhenyu Hu

IPC: H01L29/66 ,  H01L21/285 ,  H01L21/762 ,  H01L29/06 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/28518 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/7851

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to single fin structures and methods of manufacture. The structure includes: an active single fin structure; a plurality of dummy fin structures on opposing sides of the active single fin structure; source and drain regions formed on the active single fin structure and the dummy fin structures; recessed shallow trench isolation (STI) regions between the dummy fin structures and the active single fin structure and below a surface of the dummy fin structures; and contacts formed on the source and drain regions of the active single fin structure with a spacing of at least two dummy fin structures on opposing sides of the contacts.