SYNTHESIZABLE LOGIC MEMORY
    1.
    发明公开

    公开(公告)号:US20230186980A1

    公开(公告)日:2023-06-15

    申请号:US17546408

    申请日:2021-12-09

    CPC classification number: G11C11/419 G06F30/327 G06F30/3315 G11C11/412

    Abstract: Embodiments of the present disclosure provide a method for forming a memory, including: forming a memory core using a plurality of cells from a library of cells, wherein each cell in the library of cells follows standard cell row placement constraints and includes a static timing model, and wherein the plurality of cells includes a dynamic bitcell; wherein forming the memory core further includes connecting a plurality of the bitcells via abutment to form a rectangular array of bitcells such that bitlines of the bitcells and wordlines of the bitcells connect by abutment and are shared between adjacent bitcells in the array of bitcells.

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