公开(公告)号：US20230422519A1

公开(公告)日：2023-12-28

申请号：US17847776

申请日：2022-06-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Venkatesh P. Gopinath ,  Joseph Versaggi ,  Gregory A. Northrop ,  Bipul C. Paul

IPC: H01L27/24 ,  G11C5/10 ,  H01L45/00

CPC classification number: H01L27/2436 ,  G11C5/10 ,  H01L45/16

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a capacitor integrated with a memory element of a memory cell and methods of manufacture. The structure includes: at least one memory cell comprising a memory element with a top conductor material; and a capacitor connected to the memory element by the top conductor material.

公开(公告)号：US11043418B2

公开(公告)日：2021-06-22

申请号：US16685648

申请日：2019-11-15

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Jason E. Stephens ,  Daniel Chanemougame ,  Ruilong Xie ,  Lars W. Liebmann ,  Gregory A. Northrop

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of the line self-aligned direct pattern contacts and methods of manufacture. The structures described herein include: at least one gate structure with a metallization and source/drain regions; a source/drain contact in electrical connection with the source/drain regions, respectively; and a contact structure with a re-entrant profile in electrical connection with the source/drain contact and the metallization of the at least one gate structure, respectively.

公开(公告)号：US20230186980A1

公开(公告)日：2023-06-15

申请号：US17546408

申请日：2021-12-09

Applicant: GlobalFoundries U.S. Inc.

Inventor： Gregory A. Northrop ,  Vivek Raj ,  Amlan Bag ,  Shashank Nemawarkar

IPC: G11C11/419 ,  G06F30/327 ,  G06F30/3315

CPC classification number: G11C11/419 ,  G06F30/327 ,  G06F30/3315 ,  G11C11/412

Abstract: Embodiments of the present disclosure provide a method for forming a memory, including: forming a memory core using a plurality of cells from a library of cells, wherein each cell in the library of cells follows standard cell row placement constraints and includes a static timing model, and wherein the plurality of cells includes a dynamic bitcell; wherein forming the memory core further includes connecting a plurality of the bitcells via abutment to form a rectangular array of bitcells such that bitlines of the bitcells and wordlines of the bitcells connect by abutment and are shared between adjacent bitcells in the array of bitcells.

公开(公告)号：US11635958B1

公开(公告)日：2023-04-25

申请号：US17567209

申请日：2022-01-03

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vivek Raj ,  Gregory A. Northrop ,  Shashank Nemawarkar ,  Shivraj Gurpadappa Dharne

IPC: G06F9/30 ,  G06F7/544

Abstract: Embodiments of the present disclosure provide a multi-port register file, including: a plurality of single-bit data registers for receiving and storing input data; a read path coupled to an output of each of the plurality of data registers; a plurality of AND gates, wherein an output of each of the plurality of data registers is coupled to an input of a respective AND gate of the plurality of AND gates; an input gating signal coupled to another input of each of the plurality of AND gates; a plurality of multi-bit registers, wherein an output of each of the plurality of AND gates is coupled to each of the plurality of multi-bit registers; and a write disable circuit coupled to the input gating signal for disabling a write signal applied to each of the plurality of multi-bit registers.