公开(公告)号：US12093730B2

公开(公告)日：2024-09-17

申请号：US18476690

申请日：2023-09-28

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Dejan S. Milojicic ,  Kimberly Keeton ,  Paolo Faraboschi ,  Cullen E. Bash

IPC: G06F9/48 ,  G06F9/50

CPC classification number: G06F9/4881 ,  G06F9/5005 ,  G06F9/5044 ,  G06F9/505 ,  G06F9/5055

Abstract: Systems and methods are provided for incorporating an optimized dispatcher with an FaaS infrastructure to permit and restrict access to resources. For example, the dispatcher may assign requests to “warm” resources and initiate a fault process if the resource is overloaded or a cache-miss is identified (e.g., by restarting or rebooting the resource). The warm instances or accelerators associated with the allocation size that are identified may be commensurate to the demand and help dynamically route requests to faster accelerators.

公开(公告)号：US11809218B2

公开(公告)日：2023-11-07

申请号：US17198871

申请日：2021-03-11

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Dejan S. Milojicic ,  Kimberly Keeton ,  Paolo Faraboschi ,  Cullen E. Bash

IPC: G06F9/48 ,  G06F9/50

CPC classification number: G06F9/4881 ,  G06F9/505 ,  G06F9/5005 ,  G06F9/5044 ,  G06F9/5055

Abstract: Systems and methods are provided for incorporating an optimized dispatcher with an FaaS infrastructure to permit and restrict access to resources. For example, the dispatcher may assign requests to “warm” resources and initiate a fault process if the resource is overloaded or a cache-miss is identified (e.g., by restarting or rebooting the resource). The warm instances or accelerators associated with the allocation size that are identified may be commensurate to the demand and help dynamically route requests to faster accelerators.

公开(公告)号：US20180322158A1

公开(公告)日：2018-11-08

申请号：US15585153

申请日：2017-05-02

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Huanchen Zhang ,  Kimberly Keeton

IPC: G06F17/30

CPC classification number: G06F17/30362 ,  G06F17/30353 ,  G06F17/30356

Abstract: Example implementations relate to changing concurrency control modes. An example implementation includes controlling a concurrency control mode of a data slot that stores a data value. A concurrency control mode of a data slot may be changed from an optimistic concurrency control mode to a multi-version concurrency control mode responsive to detecting a read-write conflict for the data slot. A concurrency control mode of a data slot may be changed from a multi-version concurrency control mode to an optimistic concurrency control mode responsive to detecting that the data slot satisfies a low contention criterion.

公开(公告)号：US20220291952A1

公开(公告)日：2022-09-15

申请号：US17198871

申请日：2021-03-11

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： DEJAN S. MILOJICIC ,  Kimberly Keeton ,  Paolo Faraboschi ,  Cullen E. Bash

IPC: G06F9/48 ,  G06F9/50

Abstract: Systems and methods are provided for incorporating an optimized dispatcher with an FaaS infrastructure to permit and restrict access to resources. For example, the dispatcher may assign requests to “warm” resources and initiate a fault process if the resource is overloaded or a cache-miss is identified (e.g., by restarting or rebooting the resource). The warm instances or accelerators associated with the allocation size that are identified may be commensurate to the demand and help dynamically route requests to faster accelerators.

公开(公告)号：US11144237B2

公开(公告)日：2021-10-12

申请号：US16529142

申请日：2019-08-01

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Milind M. Chabbi ,  Yupu Zhang ,  Haris Volos ,  Kimberly Keeton

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/1072 ,  G06F12/1081 ,  G06F13/00 ,  G06F13/28

Abstract: Systems and methods for concurrent reading and writing in shared, persistent byte-addressable non-volatile memory is described herein. One method includes in response to initiating a write sequence to one or more memory elements, checking an identifier memory element to determine whether a write sequence is in progress. In addition, the method includes updating an ingress counter. The method also includes adding process identification associated with a writer node to the identifier memory element. Next, a write operation is performed. After the write operation, an egress counter is incremented and the identifier memory element is reset to an expected value.

公开(公告)号：US10997064B2

公开(公告)日：2021-05-04

申请号：US16453784

申请日：2019-06-26

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Sanketh Nalli ,  Haris Volos ,  Kimberly Keeton

IPC: G06F12/02 ,  G06F12/0804 ,  G06F12/0868

Abstract: Examples relate to ordering updates for nonvolatile memory accesses. In some examples, a first update that is propagated from a write-through processor cache of a processor is received by a write ordering buffer, where the first update is associated with a first epoch. The first update is stored in a first buffer entry of the write ordering buffer. At this stage, a second update that is propagated from the write-through processor cache is received, where the second update is associated with a second epoch. A second buffer entry of the write ordering buffer is allocated to store the second update. The first buffer entry and the second buffer entry can then be evicted to non-volatile memory in epoch order.

公开(公告)号：US20190317891A1

公开(公告)日：2019-10-17

申请号：US16453784

申请日：2019-06-26

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Sanketh Nalli ,  Haris Volos ,  Kimberly Keeton

IPC: G06F12/02 ,  G06F12/0868 ,  G06F12/0804

Abstract: Examples relate to ordering updates for nonvolatile memory accesses. In some examples, a first update that is propagated from a write-through processor cache of a processor is received by a write ordering buffer, where the first update is associated with a first epoch. The first update is stored in a first buffer entry of the write ordering buffer. At this stage, a second update that is propagated from the write-through processor cache is received, where the second update is associated with a second epoch. A second buffer entry of the write ordering buffer is allocated to store the second update. The first buffer entry and the second buffer entry can then be evicted to non-volatile memory in epoch order.

公开(公告)号：US20190102416A1

公开(公告)日：2019-04-04

申请号：US15721317

申请日：2017-09-29

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Huanchen Zhang ,  Kimberly Keeton

IPC: G06F17/30 ,  G06F3/06

CPC classification number: G06F16/2343 ,  G06F3/0619 ,  G06F3/0622 ,  G06F3/0637 ,  G06F3/067 ,  G06F9/52 ,  G06F9/522 ,  G06F9/524 ,  G06F9/526 ,  G06F13/1663 ,  G06F16/2365 ,  G06F16/2379

Abstract: A system includes processing nodes and shared memory. Each processing node includes a processor and local memory. The local memory of each processing node stores at least a partial copy of the immutable data stage of a dataset. The shared memory is accessible by each processing node and stores a sole copy of the mutable data stage of the dataset and a master copy of the immutable data stage of a dataset.

公开(公告)号：US10854331B2

公开(公告)日：2020-12-01

申请号：US15522246

申请日：2014-10-26

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Henggang Cui ,  Kimberly Keeton ,  Indrajit Roy ,  Krishnamurthy Viswanathan ,  Haris Volos

IPC: G06F16/2453 ,  G16H40/63 ,  G06F16/25 ,  G06F17/14 ,  G06F17/18

Abstract: A transformation on raw data is applied to produce transformed data, where the transformation includes at least one selected from among a summary of the raw data or a transform of the raw data between different domains. In response to a query to access data, the query is processed using the transformed data.

公开(公告)号：US10698878B2

公开(公告)日：2020-06-30

申请号：US15556238

申请日：2015-03-06

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Stanko Novakovic ,  Kimberly Keeton ,  Paolo Faraboschi ,  Robert Schreiber

IPC: G06F16/23 ,  G06F16/901 ,  G06F16/27

Abstract: In some examples, a graph processing server is communicatively linked to a shared memory. The shared memory may also be accessible to a different graph processing server. The graph processing server may compute an updated vertex value for a graph portion handled by the graph processing server and flush the updated vertex value to the shared memory, for retrieval by the different graph processing server. The graph processing server may also notify the different graph processing server indicating that the updated vertex value has been flushed to the shared memory.