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公开(公告)号：US10361731B2
公开(公告)日：2019-07-23
申请号：US15828106
申请日：2017-11-30
发明人： Zhiwei A. Xu , Yen-Cheng Kuan , Cynthia D. Baringer , Hasan Sharifi , James Chingwei Li , Donald A. Hitko
摘要： A Delta-Sigma modulator architecture is disclosed that uses interleaving and dynamic matching algorithms to address the needs of multi-mode, multi-band high bandwidth transmitters. The proposed architecture also supports a novel software defined transmitter architecture based on an interleaved Delta-Sigma modulator to generate RF signals. The proposed architecture leverages interleaving concepts to relax subcomponent clock rates without changing the effective oversampling ratio, thus, making it easier to reach aggressive dynamic range goals across wider bandwidths at higher frequencies. The DEM algorithm helps to randomize mismatch errors across all interleaved paths and improves substantially the signal-to-noise ratio. Additionally, a tunable bandpass filter can be added to reject out-of-band emissions.
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公开(公告)号：US20190165820A1
公开(公告)日：2019-05-30
申请号：US15828106
申请日：2017-11-30
发明人： Zhiwei A. Xu , Yen-Cheng Kuan , Cynthia D. Baringer , Hasan Sharifi , James Chingwei Li , Donald A. Hitko
摘要： A Delta-Sigma modulator architecture is disclosed that uses interleaving and dynamic matching algorithms to address the needs of multi-mode, multi-band high bandwidth transmitters. The proposed architecture also supports a novel software defined transmitter architecture based on an interleaved Delta-Sigma modulator to generate RF signals. The proposed architecture leverages interleaving concepts to relax subcomponent clock rates without changing the effective oversampling ratio, thus, making it easier to reach aggressive dynamic range goals across wider bandwidths at higher frequencies. The DEM algorithm helps to randomize mismatch errors across all interleaved paths and improves substantially the signal-to-noise ratio. Additionally, a tunable bandpass filter can be added to reject out-of-band emissions.
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公开(公告)号：US09705519B1
公开(公告)日：2017-07-11
申请号：US15196496
申请日：2016-06-29
发明人： Cynthia D. Baringer
CPC分类号： H03M7/3073 , H03K5/00 , H03K5/1565
摘要： A circuit for correcting time encoder errors including a time encoder having a time encoder input, a time encoder output, and a current summing point, and a pulse width modifier coupled to the time encoder output, the pulse width modifier having a current output coupled to the current summing point, and having a corrected output. The pulse width modifier is configured to calibrate duty cycle errors and nonlinearity errors on the time encoder output, to correct the duty cycle errors and the nonlinearity errors on the time encoder output, and to output the corrected output.
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公开(公告)号：US09621183B2
公开(公告)日：2017-04-11
申请号：US14745354
申请日：2015-06-19
申请人： HRL LABORATORIES LLC
摘要： A delta sigma modulator which has improved the dynamic range. The ΔΣ modulator has a plurality of ADCs and a plurality of DACs, the plurality of ADCs and DACs are connected in a loop. The plurality of ADCs are coupled with an incoming analog signal. A clock generator provides a plurality of clock signals which control the plurality of ADCs and the plurality of DACs, the clock signals being offset relative to each other in the time domain thereby enabling each ADC in the plurality of ADCs one at a time and each DAC in the plurality of DACs one at a time so that the ΔΣ modulator processes data in the incoming analog signal in an interleaved fashion. The delta sigma modulator has an Nth order filter in a forward path of the loop.
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