Method for operating a ferroelectric of electret memory device, and a device of this kind
    1.
    发明授权
    Method for operating a ferroelectric of electret memory device, and a device of this kind 有权
    操作驻极体存储装置的铁电体的方法以及这种装置

    公开(公告)号:US06937500B2

    公开(公告)日:2005-08-30

    申请号:US10659428

    申请日:2003-09-11

    IPC分类号: G11C11/22

    CPC分类号: G11C11/22

    摘要: A matrix-addressable ferroelectric or electret memory device and a method of operating are explained. The method includes applying a first plurality of voltage difference across a first and a second set of electrodes in the memory when data are read, and applying a second plurality of voltage differences when data are refreshed or rewritten. The first and second plurality of voltage differences correspond to sets of potential levels comprising time sequences of voltage pulses. At least one parameter indicative of a change in a memory cell response is used for determining at least one correction factor for the voltage pulses, whereby the pulse parameter is adjusted accordingly. The memory device comprises means for determining the at least one parameter, a calibration memory connected with means for determining the correction factor, and control circuits for adjusting pulse parameters as applied to read and write operations in the memory device.

    摘要翻译: 说明矩阵寻址铁电或驻极体存储器件及其操作方法。 该方法包括当读取数据时在存储器中的第一和第二组电极上施加第一多个电压差,以及当刷新或重写数据时施加第二多个电压差。 第一和第二多个电压差对应于包括电压脉冲的时间序列的电位电平集合。 指示存储器单元响应的变化的至少一个参数用于确定电压脉冲的至少一个校正因子,从而相应地调整脉冲参数。 存储器件包括用于确定至少一个参数的装置,与用于确定校正因子的装置连接的校准存储器以及用于调整应用于存储器件中的读和写操作的脉冲参数的控制电路。

    Method for performing write and read operations in a passive matrix memory, and apparatus for performing the method
    2.
    发明授权
    Method for performing write and read operations in a passive matrix memory, and apparatus for performing the method 有权
    在无源矩阵存储器中执行写入和读取操作的方法,以及用于执行该方法的装置

    公开(公告)号:US06606261B2

    公开(公告)日:2003-08-12

    申请号:US09899094

    申请日:2001-07-06

    IPC分类号: G11C1112

    CPC分类号: G11C11/22

    摘要: A method and apparatus for performing read and write operations in matrix-addressed memory array of memory cells is described. The memory cells comprising an electrically polarizable material exhibiting polarization remanence, in particular and electret or ferroelectric material, where a logical value stored in a memory cell is represented by an actual polarization state in the memory cell. The degree of polarization in the polarizable material is limited during each read and write cycle to a value defined by a circuit device controlling the read and write operations, with said value ranging from zero to an upper limit corresponding to saturation of the polarization and consistent with predetermined criterta for a reliable detection of a logic state of a memory cell.

    摘要翻译: 描述了一种在存储器单元的矩阵寻址存储器阵列中执行读和写操作的方法和装置。 存储单元包括表现出极化剩磁的电可极化材料,特别是驻极体或铁电材料,其中存储在存储单元中的逻辑值由存储单元中的实际极化状态表示。 在每个读取和写入周期期间,可极化材料中的极化程度被限制在由控制读取和写入操作的电路装置定义的值,所述值范围从零到上限,对应于极化饱和度,并与 用于可靠地检测存储器单元的逻辑状态的预定标准。

    Method for operating a passive matrix-addressable ferroelectric or electret memory device
    3.
    发明授权
    Method for operating a passive matrix-addressable ferroelectric or electret memory device 失效
    用于操作无源矩阵寻址铁电或驻极体存储器件的方法

    公开(公告)号:US07215565B2

    公开(公告)日:2007-05-08

    申请号:US11027977

    申请日:2005-01-04

    IPC分类号: G11C11/22

    CPC分类号: G11C29/50 G11C11/22

    摘要: In a method for operating a passive matrix-addressable ferroelectric or electret memory device, a voltage pulse protocol based on a 1/3 voltage selection rule is used in order to keep disturb voltages at minimum, the voltage pulse protocol comprising cycles for read and write/erase bases on time sequence of voltage pulses with defined parameters. The method comprises a refresh procedure wherein cells for refresh are selected and refresh requests processed by a memory device controller, the refresh requests are monitored and processed in regard of ongoing or scheduled memory operations, and refresh voltage pulses with defined parameters are applied to the memory cells selected for refresh, while simultaneously ensuring that non-selected memory cells are subjected to zero voltage or voltages which do not affect the polarization state of these cells.

    摘要翻译: 在用于操作无源矩阵寻址铁电或驻极体存储器件的方法中,使用基于1/3电压选择规则的电压脉冲协议以便将干扰电压保持在最小值,所述电压脉冲协议包括用于读取和写入的周期 根据具有定义参数的电压脉冲的时间顺序进行擦除。 该方法包括刷新过程,其中选择用于刷新的单元和由存储器件控制器处理的刷新请求,关于正在进行或调度的存储器操作来监视和处理刷新请求,并且将具有所定义参数的刷新电压脉冲施加到存储器 选择用于刷新的单元,同时确保未选择的存储单元经受不影响这些单元的极化状态的零电压或电压。

    Method for operating a ferroelectric of electret memory device, and a device of this kind

    公开(公告)号:US20050073869A1

    公开(公告)日:2005-04-07

    申请号:US10659428

    申请日:2003-09-11

    IPC分类号: G11C11/22

    CPC分类号: G11C11/22

    摘要: A matrix-addressable ferroelectric or electret memory device and a method of operating are explained. The method includes applying a first plurality of voltage difference across a first and a second set of electrodes in the memory when data are read, and applying a second plurality of voltage differences when data are refreshed or rewritten. The first and second plurality of voltage differences correspond to sets of potential levels comprising time sequences of voltage pulses. At least one parameter indicative of a change in a memory cell response is used for determining at least one correction factor for the voltage pulses, whereby the pulse parameter is adjusted accordingly. The memory device comprises means for determining the at least one parameter, a calibration memory connected with means for determining the correction factor, and control circuits for adjusting pulse parameters as applied to read and write operations in the memory device.

    Method for operating a passive matrix-addressable ferroelectric or electret memory device
    6.
    发明申请
    Method for operating a passive matrix-addressable ferroelectric or electret memory device 失效
    用于操作无源矩阵寻址铁电或驻极体存储器件的方法

    公开(公告)号:US20060146589A1

    公开(公告)日:2006-07-06

    申请号:US11027977

    申请日:2005-01-04

    IPC分类号: G11C11/22

    CPC分类号: G11C29/50 G11C11/22

    摘要: In a method for operating a passive matrix-addressable ferroelectric or electret memory device, a voltage pulse protocol based on a 1/3 voltage selection rule is used in order to keep disturb voltages at minimum, the voltage pulse protocol comprising cycles for read and write/erase bases on time sequence of voltage pulses with defined parameters. The method comprises a refresh procedure wherein cells for refresh are selected and refresh requests processed by a memory device controller, the refresh requests are monitored and processed in regard of ongoing or scheduled memory operations, and refresh voltage pulses with defined parameters are applied to the memory cells selected for refresh, while simultaneously ensuring that non-selected memory cells are subjected to zero voltage or voltages which do not affect the polarization state of these cells.

    摘要翻译: 在用于操作无源矩阵寻址铁电或驻极体存储器件的方法中,使用基于1/3电压选择规则的电压脉冲协议以便将干扰电压保持在最小值,所述电压脉冲协议包括用于读取和写入的周期 根据具有定义参数的电压脉冲的时间顺序进行擦除。 该方法包括刷新过程,其中选择用于刷新的单元和由存储器件控制器处理的刷新请求,关于正在进行或调度的存储器操作来监视和处理刷新请求,并且将具有所定义参数的刷新电压脉冲施加到存储器 选择用于刷新的单元,同时确保未选择的存储单元经受不影响这些单元的极化状态的零电压或电压。

    Methods and arrangements including circuit breaking means in a power supply system
    9.
    发明授权
    Methods and arrangements including circuit breaking means in a power supply system 有权
    包括电源系统中断路装置的方法和装置

    公开(公告)号:US08767363B2

    公开(公告)日:2014-07-01

    申请号:US13516300

    申请日:2009-12-18

    IPC分类号: H02H3/00

    CPC分类号: H02H3/087 H02H3/081

    摘要: Power modules and related methods are providing configured to supply power from a power source to a power consuming unit. The power module configured to disconnect power in the power module in case of excess currents through the circuit breakers.

    摘要翻译: 功率模块和相关方法被配置为从电源向功耗单元供电。 电源模块配置为在通过断路器的电流过大的情况下断开电源模块中的电源。