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1.发明授权Method of manufacturing semiconductor integrated circuit device with high and low breakdown-voltage MISFETs 有权具有高和低击穿电压MISFET的半导体集成电路器件的制造方法公开(公告)号：US07790554B2
公开(公告)日：2010-09-07
申请号：US12432393
申请日：2009-04-29
IPC分类号： H01L21/77
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823857 , H01L21/823892 , H01L27/0629 , H01L27/092 , Y10S438/981
摘要： Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the second region. The present invention makes it possible to raise the threshold voltage of a parasitic MOS and in addition, to suppress occurrence of an NBT phenomenon.
摘要翻译： 提供一种半导体集成电路器件的制造方法，该半导体集成电路器件在第一区域具有多个第一MISFET以及第二区域中的多个第二MISFET，其包括在第一MISFET形成区域的两个相邻区域之间形成第一绝缘膜， 在第二区域中的第一区域和第二MISFET形成区域; 在所述第一和第二区域中的每个中的所述第一绝缘膜之间的所述半导体衬底的表面上形成第二绝缘膜; 在所述第二绝缘膜上沉积第三绝缘膜; 在所述第二区域中在所述第三绝缘膜上形成第一导电膜; 在从所述第一区域去除所述第三绝缘膜和所述第二绝缘膜之后，在所述第一区域中的所述半导体衬底的表面上形成第四绝缘膜; 以及在所述第四绝缘膜上形成第二导电膜; 其中所述第三绝缘膜保留在所述第二区域中的所述第一绝缘膜上。 本发明使得可以提高寄生MOS的阈值电压，并且还抑制NBT现象的发生。
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2.发明授权Semiconductor integrated circuit device with high and low breakdown-voltage MISFETs 有权具有高和低击穿电压MISFET的半导体集成电路器件公开(公告)号：US07541661B2
公开(公告)日：2009-06-02
申请号：US11614469
申请日：2006-12-21
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823857 , H01L21/823892 , H01L27/0629 , H01L27/092 , Y10S438/981
摘要： Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the second region. The present invention makes it possible to raise the threshold voltage of a parasitic MOS and in addition, to suppress occurrence of an NBT phenomenon.
摘要翻译： 提供一种半导体集成电路器件的制造方法，该半导体集成电路器件在第一区域具有多个第一MISFET以及第二区域中的多个第二MISFET，其包括在第一MISFET形成区域的两个相邻区域之间形成第一绝缘膜， 在第二区域中的第一区域和第二MISFET形成区域; 在所述第一和第二区域中的每个中的所述第一绝缘膜之间的半导体衬底的表面上形成第二绝缘膜; 在所述第二绝缘膜上沉积第三绝缘膜; 在所述第二区域中在所述第三绝缘膜上形成第一导电膜; 在从所述第一区域去除所述第三绝缘膜和所述第二绝缘膜之后，在所述第一区域中的所述半导体衬底的表面上形成第四绝缘膜; 以及在所述第四绝缘膜上形成第二导电膜; 其中所述第三绝缘膜保留在所述第二区域中的所述第一绝缘膜上。 本发明使得可以提高寄生MOS的阈值电压，并且还抑制NBT现象的发生。
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3.发明授权Semiconductor integrated circuit device with high and low breakdown-voltage MISFETs 有权具有高和低击穿电压MISFET的半导体集成电路器件公开(公告)号：US07224037B2
公开(公告)日：2007-05-29
申请号：US10894019
申请日：2004-07-20
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823857 , H01L21/823892 , H01L27/0629 , H01L27/092 , Y10S438/981
摘要： Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the second region. The present invention makes it possible to raise the threshold voltage of a parasitic MOS and in addition, to suppress occurrence of an NBT phenomenon.
摘要翻译： 提供一种半导体集成电路器件的制造方法，该半导体集成电路器件在第一区域具有多个第一MISFET以及第二区域中的多个第二MISFET，其包括在第一MISFET形成区域的两个相邻区域之间形成第一绝缘膜， 在第二区域中的第一区域和第二MISFET形成区域; 在所述第一和第二区域中的每个中的所述第一绝缘膜之间的所述半导体衬底的表面上形成第二绝缘膜; 在所述第二绝缘膜上沉积第三绝缘膜; 在所述第二区域中在所述第三绝缘膜上形成第一导电膜; 在从所述第一区域去除所述第三绝缘膜和所述第二绝缘膜之后，在所述第一区域中的所述半导体衬底的表面上形成第四绝缘膜; 以及在所述第四绝缘膜上形成第二导电膜; 其中所述第三绝缘膜保留在所述第二区域中的所述第一绝缘膜上。 本发明使得可以提高寄生MOS的阈值电压，并且还抑制NBT现象的发生。
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4.发明申请公开(公告)号：US20070096247A1
公开(公告)日：2007-05-03
申请号：US11614469
申请日：2006-12-21
IPC分类号： H01L29/00
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823857 , H01L21/823892 , H01L27/0629 , H01L27/092 , Y10S438/981
摘要： Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the second region. The present invention makes it possible to raise the threshold voltage of a parasitic MOS and in addition, to suppress occurrence of an NBT phenomenon.
摘要翻译： 提供一种半导体集成电路器件的制造方法，该半导体集成电路器件在第一区域具有多个第一MISFET以及第二区域中的多个第二MISFET，其包括在第一MISFET形成区域的两个相邻区域之间形成第一绝缘膜， 在第二区域中的第一区域和第二MISFET形成区域; 在所述第一和第二区域中的每个中的所述第一绝缘膜之间的所述半导体衬底的表面上形成第二绝缘膜; 在所述第二绝缘膜上沉积第三绝缘膜; 在所述第二区域中在所述第三绝缘膜上形成第一导电膜; 在从所述第一区域去除所述第三绝缘膜和所述第二绝缘膜之后，在所述第一区域中的所述半导体衬底的表面上形成第四绝缘膜; 以及在所述第四绝缘膜上形成第二导电膜; 其中所述第三绝缘膜保留在所述第二区域中的所述第一绝缘膜上。 本发明使得可以提高寄生MOS的阈值电压，并且还抑制NBT现象的发生。
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公开(公告)号：US06780717B2
公开(公告)日：2004-08-24
申请号：US09989061
申请日：2001-11-21
IPC分类号： H01L218236
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823857 , H01L21/823892 , H01L27/0629 , H01L27/092 , Y10S438/981
摘要： Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the second region. The present invention makes it possible to raise the threshold voltage of a parasitic MOS and in addition, to suppress occurrence of an NBT phenomenon.
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6.发明申请公开(公告)号：US20090209078A1
公开(公告)日：2009-08-20
申请号：US12432393
申请日：2009-04-29
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823857 , H01L21/823892 , H01L27/0629 , H01L27/092 , Y10S438/981
摘要： Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the second region. The present invention makes it possible to raise the threshold voltage of a parasitic MOS and in addition, to suppress occurrence of an NBT phenomenon.
摘要翻译： 提供一种半导体集成电路器件的制造方法，该半导体集成电路器件在第一区域具有多个第一MISFET以及第二区域中的多个第二MISFET，其包括在第一MISFET形成区域的两个相邻区域之间形成第一绝缘膜， 在第二区域中的第一区域和第二MISFET形成区域; 在所述第一和第二区域中的每个中的所述第一绝缘膜之间的半导体衬底的表面上形成第二绝缘膜; 在所述第二绝缘膜上沉积第三绝缘膜; 在所述第二区域中在所述第三绝缘膜上形成第一导电膜; 在从所述第一区域去除所述第三绝缘膜和所述第二绝缘膜之后，在所述第一区域中的所述半导体衬底的表面上形成第四绝缘膜; 以及在所述第四绝缘膜上形成第二导电膜; 其中所述第三绝缘膜保留在所述第二区域中的所述第一绝缘膜上。 本发明使得可以提高寄生MOS的阈值电压，并且还抑制NBT现象的发生。
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公开(公告)号：US20050007508A1
公开(公告)日：2005-01-13
申请号：US10886636
申请日：2004-07-09
IPC分类号： G02F1/1333 , G02F1/1335 , G02F1/1343 , G02F1/1362 , G09F9/30 , H01L51/50
CPC分类号： G02F1/136227 , G02F1/133553
摘要： A display device has plural pixel areas on the substrate. Each of the pixel areas has a pixel electrode and a multilevel structure disposed below the pixel electrode. The multilevel structure includes a first conductive layer, a first insulating film, a second conductive layer, a second insulating film, and a third conductive layer stacked in this order from the substrate. A solid electrical conductor is buried to fill a through-hole in the first insulating film to contact the first conductive layer, the second conductive layer is provided with a hole larger in diameter than the conductor, and the second insulating film is provided with a through-hole larger in diameter than the conductor, but smaller in diameter than the hole in the second conductive layer, and the third conductive layer is coated on the second insulating film to contact the conductor via the through-hole in the second insulating film.
摘要翻译： 显示装置在基板上具有多个像素区域。 每个像素区域具有像素电极和设置在像素电极下方的多层结构。 多层结构包括从衬底依次堆叠的第一导电层，第一绝缘膜，第二导电层，第二绝缘膜和第三导电层。 埋入固体电导体以填充第一绝缘膜中的通孔以接触第一导电层，第二导电层设置有直径大于导体的孔，并且第二绝缘膜设置有通孔 直径比导体大，但直径小于第二导电层中的孔，并且第三导电层涂覆在第二绝缘膜上，以经由第二绝缘膜中的通孔与导体接触。
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8.发明申请公开(公告)号：US20080054272A1
公开(公告)日：2008-03-06
申请号：US11896682
申请日：2007-09-05
申请人： Nobuya Sato , Kazunari Saitou
发明人： Nobuya Sato , Kazunari Saitou
CPC分类号： H01S5/22 , B82Y20/00 , H01L33/0079 , H01L33/20 , H01S5/0425 , H01S5/34306 , H01S5/4018 , H01S5/4031 , H01S5/405
摘要： A semiconductor light-emitting device capable of preventing fusion bonding between electrodes or damage to an electrode, and a method of manufacturing the same are provided. A semiconductor light-emitting device includes a semiconductor layer and a first electrode on a first surface of a semiconductor substrate in order from the semiconductor substrate side and a second electrode on a second surface of the semiconductor substrate, the semiconductor layer including a light-emitting region, the first electrode being arranged corresponding to at least the light-emitting region, wherein a recessed section with a depth larger than the thickness of the second electrode in arranged on the second surface, thereby a step section projected from the recessed section is formed in a region other than the recessed section in the second surface, and the second electrode is formed on a least the recessed section of the second surface.
摘要翻译： 提供了能够防止电极之间的熔合或电极损坏的半导体发光装置及其制造方法。 半导体发光器件包括半导体层和半导体衬底的第一表面上的半导体衬底侧的顺序的第一电极和半导体衬底的第二表面上的第二电极，所述半导体层包括发光 区域，所述第一电极被布置为至少对应于所述发光区域，其中形成有深度大于设置在所述第二表面上的所述第二电极的厚度的凹陷部分，从而形成从所述凹部突出的台阶部分 在除了第二表面中的凹陷部分之外的区域中，并且第二电极形成在第二表面的至少凹部上。
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公开(公告)号：US07102609B2
公开(公告)日：2006-09-05
申请号：US10125363
申请日：2002-04-19
IPC分类号： G09G3/36
CPC分类号： G09G3/3685 , G09G3/3614 , G09G3/3688 , G09G2310/027 , G09G2330/021 , G09G2370/08
摘要： The present invention realizes a liquid crystal display which mounts driving circuits of low power consumption on a substrate on which a display part is mounted. The driving circuits which supply gray scale voltages to pixels are mounted on a liquid crystal display panel. Display data is transferred between the driving circuits using wiring formed on the liquid crystal display panel, the display data is transferred in the inside of the driving circuits through inner data bus lines, and a data inversion calculation which inverts values of the display data is performed in the inside of the driving circuits for achieving the low power consumption.
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