公开(公告)号：US06212236B1

公开(公告)日：2001-04-03

申请号：US09048190

申请日：1998-03-25

申请人： Hideshi Nishida ,  Kozo Kimura ,  Makoto Hirai ,  Tokuzo Kiyohara

发明人： Hideshi Nishida ,  Kozo Kimura ,  Makoto Hirai ,  Tokuzo Kiyohara

IPC分类号： H04N712

CPC分类号： H04N19/507 ,  H04N19/61

摘要： Bitstream analyzing unit 111 fetches a coded block pattern and a coded quantized DCT coefficient from each block in a bitstream. Entropy decoding unit 112 decodes the coded block pattern into a block pattern and decodes the coded quantized DCT coefficient into pairs of a run length and an effectiveness factor. Dequantization unit 115 generates orthogonal transformation coefficients from the pairs of a run length and an effectiveness factor. Inverse Discrete Cosine Transform (IDCT) unit 110 generates a difference image from the orthogonal transformation coefficients. Decode controlling unit 110 instructs first selecting unit 118 to select constants “0”output from first constant generating unit 117 when the image is a “skipped” block. Image storage unit 120 stores a plurality of reference frame pictures having been decoded. Image restoring unit 119 restores an original block by adding a decoded difference image to a reference block read from the reference frame pictures stored in the image storage unit 120.

摘要翻译： 比特流分析单元111从比特流中的每个块获取编码块模式和编码的量化DCT系数。 熵解码单元112将编码块模式解码为块模式，并将编码的量化DCT系数解码为游程长度和有效性因子对。 去量化单元115从游程长度和有效性因子的对生成正交变换系数。 逆离散余弦变换（IDCT）单元110从正交变换系数生成差分图像。 当图像为“跳过”块时，解码控制单元110指示第一选择单元118选择从第一常数生成单元117输出的常数“0”。 图像存储单元120存储已被解码的多个参考帧图像。 图像恢复单元119通过将解码的差异图像添加到从存储在图像存储单元120中的参考帧图像中读取的参考块来恢复原始块。

公开(公告)号：US06829302B2

公开(公告)日：2004-12-07

申请号：US10019498

申请日：2001-12-20

申请人： Hiroyuki Morishita ,  Kosuke Yoshioka ,  Hideshi Nishida ,  Makoto Hirai ,  Ryuji Matsuura ,  Toshiaki Tsuji ,  Kozo Kimura ,  Tokuzo Kiyohara

发明人： Hiroyuki Morishita ,  Kosuke Yoshioka ,  Hideshi Nishida ,  Makoto Hirai ,  Ryuji Matsuura ,  Toshiaki Tsuji ,  Kozo Kimura ,  Tokuzo Kiyohara

IPC分类号： H04N712

CPC分类号： H04N19/80 ,  G06T3/4007 ,  G06T3/4023 ,  G06T5/20 ,  G06T2200/28

摘要： A pixel calculating device that performs vertical filtering on pixel data in order to reduce frame data in a vertical direction. The pixel calculating device includes a decoding unit 401 for decoding compressed video data to produce frame data, frame memory 402 for storing the frame data, a filtering unit 403 for reducing the frame data in a vertical direction by the vertical filtering to produce a reduced image, buffer memory 404 for storing the reduced image outputted from filtering unit 403, and a control unit 406 for controlling filtering unit 403 based on a decoding state of the video data by decoding unit 401 and a filtering state of the frame data by filtering unit 403, so that overrun and underrun do not occur in filtering unit 403.

摘要翻译： 一种对像素数据进行垂直滤波以便在垂直方向上减少帧数据的像素计算装置。 像素计算装置包括用于解码压缩视频数据以产生帧数据的解码单元401，用于存储帧数据的帧存储器402，用于通过垂直滤波减少垂直方向上的帧数据以产生缩小图像的滤波单元403 用于存储从滤波单元403输出的缩小图像的缓冲存储器404，以及基于解码单元401的视频数据的解码状态和滤波单元403的帧数据的滤波状态来控制滤波单元403的控制单元406 ，因此在过滤单元403中不会发生溢出和欠载。

公开(公告)号：US06809777B2

公开(公告)日：2004-10-26

申请号：US10019419

申请日：2001-12-18

申请人： Hiroyuki Oka ,  Hideshi Nishida ,  Kosuke Yoshioka ,  Tokuzo Kiyohara ,  Makoto Hirai ,  Kozo Kimura ,  Ryuji Matsuura ,  Hiroyuki Morishita ,  Toshiaki Tsuji

发明人： Hiroyuki Oka ,  Hideshi Nishida ,  Kosuke Yoshioka ,  Tokuzo Kiyohara ,  Makoto Hirai ,  Kozo Kimura ,  Ryuji Matsuura ,  Hiroyuki Morishita ,  Toshiaki Tsuji

IPC分类号： H04N964

CPC分类号： H04N19/80 ,  G06T1/20 ,  G06T5/20

摘要： A pixel calculating device for performing vertical filtering that includes 16 pixel processing units 1 to 16 and an input buffer group 22 storing 16 pieces of pixel data and filter coefficients. Each of the pixel processing units performs operations using the pixel data and a filter coefficient supplied from input buffer group 22, and then acquires pixel data from an adjacent pixel processing unit. Further operations are performed by each of the pixel processing units using the acquired pixel data and operation results are accumulated. Filtering is carried out through a repetition of this acquiring and accumulation process, the number of taps being determined by the number of repetitions.

摘要翻译： 用于执行垂直滤波的像素计算装置，其包括16个像素处理单元1至16以及存储16个像素数据和滤波器系数的输入缓冲器组22。 每个像素处理单元使用从输入缓冲器组22提供的像素数据和滤波器系数来执行操作，然后从邻近的像素处理单元获取像素数据。 使用所获取的像素数据由每个像素处理单元执行进一步的操作，并且累积运算结果。 通过重复该获取和累积过程来进行过滤，抽头的数量由重复次数确定。

公开(公告)号：US06340973B1

公开(公告)日：2002-01-22

申请号：US09244036

申请日：1999-02-04

申请人： Toshiyuki Ochiai ,  Yosuke Furukawa ,  Yutaka Tanaka ,  Kozo Kimura ,  Makoto Hirai ,  Tokuzo Kiyohara ,  Hideshi Nishida

发明人： Toshiyuki Ochiai ,  Yosuke Furukawa ,  Yutaka Tanaka ,  Kozo Kimura ,  Makoto Hirai ,  Tokuzo Kiyohara ,  Hideshi Nishida

IPC分类号： G06F13372

CPC分类号： G06F13/1647 ,  G11C7/1072 ,  G11C7/22

摘要： A transfer-target unit outputs commands for data reading and data writing. An address generator generates control signals in accordance with the commands, and outputs the number of bytes of data first transferred by read access. A command generator generates control commands in accordance with the control signals to control an SDRAM. At this time the command generator judges the number of transferred bytes to control so that the SDRAM executes instructions in order from an instruction which is the most efficient in data transfer. That is, in the case where data is read across a bank boundary, the command generator judges which is to be executed first between read processing in a bank 0 and active processing in a bank1, to control the SDRAM. A data processor mediates data transfer between the transfer-target unit and the SDRAM in accordance with the control commands. In this way, it is possible to issue commands so as to terminate data transfer in the minimum number of cycles in the case where data read processing is continuously performed to different banks. The number of cycles required for two continuous access (access to the bank 0 and the bank 1) can be thus reduced, thereby increasing effective transfer rates of the SDRAM.

摘要翻译： 传输目标单元输出用于数据读取和数据写入的命令。 地址生成器根据命令生成控制信号，并输出通过读取访问首先传送的数据的字节数。 命令发生器根据控制信号产生控制命令以控制SDRAM。 此时，命令生成器判断要进行控制的传送字节数，使得SDRAM从数据传输中最有效的指令按顺序执行指令。 也就是说，在通过存储体边界读取数据的情况下，命令生成器判断在存储体0中的读取处理和存储体1中的有效处理之间首先执行哪个，以控制SDRAM。 数据处理器根据控制命令介入转移目标单元和SDRAM之间的数据传输。以这种方式，可以发出命令，以便在数据读取的情况下以最小数量的周期终止数据传输 不断对不同的银行进行处理。 因此可以减少两次连续访问（对存储体0和存储体1的访问）所需的周期数，从而增加SDRAM的有效传输速率。

公开(公告)号：US20080215858A1

公开(公告)日：2008-09-04

申请号：US12110539

申请日：2008-04-28

申请人： Kazuya Furukawa ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida ,  Kazushi Kurata ,  Shigeki Fujii ,  Toshio Sugimura

发明人： Kazuya Furukawa ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida ,  Kazushi Kurata ,  Shigeki Fujii ,  Toshio Sugimura

IPC分类号： G06F9/30

CPC分类号： G06F9/4881 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/462

摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

摘要翻译： 一种处理器，用于使用存储在与所述程序一对一的存储器中的多个寄存器值组来顺序地执行多个程序。 处理器包括多个寄存器组; 选择/切换单元，其可操作以选择所述多个寄存器组中的一个作为程序执行所基于的执行目标寄存器组，并且每当经过第一预定时间时切换所述选择目标; 恢复单元，其可操作以在每次执行切换时将所述寄存器值组中的一个恢复为未被选择为所述执行目标寄存器组的寄存器组之一; 保存单元，其可操作以通过重写与寄存器值相对应的存储器中的寄存器值组来在恢复之前保存用于恢复的寄存器组中的值; 以及程序执行单元，其可操作以在每次执行切换时执行与执行目标寄存器组中的寄存器值组相对应的程序。

公开(公告)号：US08006076B2

公开(公告)日：2011-08-23

申请号：US12110491

申请日：2008-04-28

申请人： Kazushi Kurata ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida ,  Kazuya Furukawa ,  Shigeki Fujii ,  Toshio Sugimura

发明人： Kazushi Kurata ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida ,  Kazuya Furukawa ,  Shigeki Fujii ,  Toshio Sugimura

IPC分类号： G06F9/48 ,  G06F9/52

CPC分类号： G06F9/4881 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/462

摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

公开(公告)号：US20090049219A1

公开(公告)日：2009-02-19

申请号：US11658816

申请日：2005-08-19

申请人： Hideshi Nishida ,  Takeshi Furuta ,  Tetsuya Tanaka ,  Kozo Kimura ,  Tokuzo Kiyohara

发明人： Hideshi Nishida ,  Takeshi Furuta ,  Tetsuya Tanaka ,  Kozo Kimura ,  Tokuzo Kiyohara

IPC分类号： G06F13/24

CPC分类号： G06F13/24 ,  G06F9/30101 ,  G06F9/3861 ,  G06F9/3879 ,  G06F9/4812 ,  G06F2209/481

摘要： To provide an information processing apparatus capable of performing switching between an exception handler and normal processing, the information processing apparatus comprising: An information processing apparatus comprising: a processor; a data processing unit operable to perform particular processing upon receiving a processing request from the processor; an interrupt controller operable to issue an interrupt request to the processor; and an exception control unit operable to control the interrupt controller, wherein the data processing unit is connected with the exception control unit via a dedicated line, the data processing unit includes a notification unit operable to notify, via the dedicated line, the exception control unit of status information showing a current status of the data processing unit, and based on the notified status information and setup information set by the processor, the exception control unit judges whether to cause the interrupt controller to issue an interrupt request to execute an exception handler to the processor.

摘要翻译： 为了提供能够执行异常处理程序与正常处理之间的切换的信息处理装置，所述信息处理装置包括：信息处理装置，包括：处理器; 数据处理单元，用于在从所述处理器接收到处理请求时执行特定处理; 中断控制器，用于向所述处理器发出中断请求; 以及异常控制单元，其可操作以控制所述中断控制器，其中所述数据处理单元经由专用线与所述异常控制单元连接，所述数据处理单元包括通知单元，用于经由所述专用线通知所述异常控制单元 表示数据处理单元的当前状态的状态信息，并且基于所通知的状态信息和由处理器设置的设置信息，异常控制单元判断是否使中断控制器发出中断请求以执行异常处理程序 处理器。

公开(公告)号：US06901454B2

公开(公告)日：2005-05-31

申请号：US10289993

申请日：2002-11-07

申请人： Nobuo Higaki ,  Tetsuya Tanaka ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida

发明人： Nobuo Higaki ,  Tetsuya Tanaka ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida

IPC分类号： G06F9/38 ,  G06F3/00 ,  G06F9/46 ,  G06F9/48 ,  G06F13/28 ,  G06F15/16 ,  G06F15/167 ,  G06F15/80

CPC分类号： G06F9/4843

摘要： A circuit group control system which receives from a master processor a first command sequence and a second command sequence each of which is composed of a plurality of commands, each command being to be executed by one of a plurality of circuits, and causes any available circuits to execute the commands one by one in order of arrangement in each command sequence. The circuit group control system achieves concurrent execution of a plurality of command sequences by causing a circuit (a second circuit) to execute a command in the second command sequence while another circuit (a first circuit) is executing another command in the first command sequence.

摘要翻译： 一种电路组控制系统，其从主处理器接收第一命令序列和第二命令序列，每个命令序列由多个命令组成，每个命令由多个电路中的一个执行，并且使任何可用的电路 按照每个命令序列中的排列顺序逐个执行命令。 电路组控制系统通过使电路（第二电路）在第二命令序列中执行命令而实现多个命令序列的并发执行，而另一电路（第一电路）在第一命令序列中执行另一命令。

公开(公告)号：US08719827B2

公开(公告)日：2014-05-06

申请号：US13179614

申请日：2011-07-11

申请人： Kazushi Kurata ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida ,  Kazuya Furukawa ,  Shigeki Fujii ,  Toshio Sugimura

发明人： Kazushi Kurata ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida ,  Kazuya Furukawa ,  Shigeki Fujii ,  Toshio Sugimura

IPC分类号： G06F9/46 ,  G06F9/00 ,  G06F1/00

CPC分类号： G06F9/4881 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/462

摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

摘要翻译： 一种处理器，用于使用存储在与所述程序一对一的存储器中的多个寄存器值组来顺序地执行多个程序。 处理器包括多个寄存器组; 选择/切换单元，其可操作以选择所述多个寄存器组中的一个作为程序执行所基于的执行目标寄存器组，并且每当经过第一预定时间时切换所述选择目标; 恢复单元，其可操作以在每次执行切换时将所述寄存器值组中的一个恢复为未被选择为所述执行目标寄存器组的寄存器组之一; 保存单元，其可操作以通过重写与寄存器值相对应的存储器中的寄存器值组来在恢复之前保存用于恢复的寄存器组中的值; 以及程序执行单元，其可操作以在每次执行切换时执行与执行目标寄存器组中的寄存器值组相对应的程序。

公开(公告)号：US07934082B2

公开(公告)日：2011-04-26

申请号：US11658816

申请日：2005-08-19

申请人： Hideshi Nishida ,  Takeshi Furuta ,  Tetsuya Tanaka ,  Kozo Kimura ,  Tokuzo Kiyohara

发明人： Hideshi Nishida ,  Takeshi Furuta ,  Tetsuya Tanaka ,  Kozo Kimura ,  Tokuzo Kiyohara

IPC分类号： G06F9/48

CPC分类号： G06F13/24 ,  G06F9/30101 ,  G06F9/3861 ,  G06F9/3879 ,  G06F9/4812 ,  G06F2209/481

摘要： An information processing apparatus performs switching between an exception handler and normal processing. The information processing apparatus includes a processor a data processing unit that performs a particular processing upon receiving a processing request from the processor; an interrupt controller that issues an interrupt request to the processor; and an exception control unit that controls the interrupt controller, wherein the data processing unit is connected with the exception control unit via a dedicated line. The data processing unit includes a notification unit that notifies, via the dedicated line, the exception control unit of status information indicating current status of the data processing unit, and based on the notified status information and setup information set by the processor, the exception control unit judges whether to cause the interrupt controller to issue to the processor an interrupt request to execute an exception handler.

摘要翻译： 信息处理装置执行异常处理程序与正常处理之间的切换。 信息处理装置包括处理器，数据处理单元，其在从处理器接收到处理请求时执行特定处理; 一个向处理器发出中断请求的中断控制器; 以及异常控制单元，其控制所述中断控制器，其中，所述数据处理单元经由专用线与所述异常控制单元连接。 数据处理单元包括：通知单元，其经由专用线通知异常控制单元，该异常控制单元指示数据处理单元的当前状态的状态信息，并且基于所通知的状态信息和由处理器设置的设置信息，异常控制 单元判断是否使中断控制器向处理器发出执行异常处理程序的中断请求。