摘要:
Bitstream analyzing unit 111 fetches a coded block pattern and a coded quantized DCT coefficient from each block in a bitstream. Entropy decoding unit 112 decodes the coded block pattern into a block pattern and decodes the coded quantized DCT coefficient into pairs of a run length and an effectiveness factor. Dequantization unit 115 generates orthogonal transformation coefficients from the pairs of a run length and an effectiveness factor. Inverse Discrete Cosine Transform (IDCT) unit 110 generates a difference image from the orthogonal transformation coefficients. Decode controlling unit 110 instructs first selecting unit 118 to select constants “0”output from first constant generating unit 117 when the image is a “skipped” block. Image storage unit 120 stores a plurality of reference frame pictures having been decoded. Image restoring unit 119 restores an original block by adding a decoded difference image to a reference block read from the reference frame pictures stored in the image storage unit 120.
摘要:
A pixel calculating device that performs vertical filtering on pixel data in order to reduce frame data in a vertical direction. The pixel calculating device includes a decoding unit 401 for decoding compressed video data to produce frame data, frame memory 402 for storing the frame data, a filtering unit 403 for reducing the frame data in a vertical direction by the vertical filtering to produce a reduced image, buffer memory 404 for storing the reduced image outputted from filtering unit 403, and a control unit 406 for controlling filtering unit 403 based on a decoding state of the video data by decoding unit 401 and a filtering state of the frame data by filtering unit 403, so that overrun and underrun do not occur in filtering unit 403.
摘要:
A pixel calculating device for performing vertical filtering that includes 16 pixel processing units 1 to 16 and an input buffer group 22 storing 16 pieces of pixel data and filter coefficients. Each of the pixel processing units performs operations using the pixel data and a filter coefficient supplied from input buffer group 22, and then acquires pixel data from an adjacent pixel processing unit. Further operations are performed by each of the pixel processing units using the acquired pixel data and operation results are accumulated. Filtering is carried out through a repetition of this acquiring and accumulation process, the number of taps being determined by the number of repetitions.
摘要:
A transfer-target unit outputs commands for data reading and data writing. An address generator generates control signals in accordance with the commands, and outputs the number of bytes of data first transferred by read access. A command generator generates control commands in accordance with the control signals to control an SDRAM. At this time the command generator judges the number of transferred bytes to control so that the SDRAM executes instructions in order from an instruction which is the most efficient in data transfer. That is, in the case where data is read across a bank boundary, the command generator judges which is to be executed first between read processing in a bank 0 and active processing in a bank1, to control the SDRAM. A data processor mediates data transfer between the transfer-target unit and the SDRAM in accordance with the control commands. In this way, it is possible to issue commands so as to terminate data transfer in the minimum number of cycles in the case where data read processing is continuously performed to different banks. The number of cycles required for two continuous access (access to the bank 0 and the bank 1) can be thus reduced, thereby increasing effective transfer rates of the SDRAM.
摘要:
A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.
摘要:
A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.
摘要:
To provide an information processing apparatus capable of performing switching between an exception handler and normal processing, the information processing apparatus comprising: An information processing apparatus comprising: a processor; a data processing unit operable to perform particular processing upon receiving a processing request from the processor; an interrupt controller operable to issue an interrupt request to the processor; and an exception control unit operable to control the interrupt controller, wherein the data processing unit is connected with the exception control unit via a dedicated line, the data processing unit includes a notification unit operable to notify, via the dedicated line, the exception control unit of status information showing a current status of the data processing unit, and based on the notified status information and setup information set by the processor, the exception control unit judges whether to cause the interrupt controller to issue an interrupt request to execute an exception handler to the processor.
摘要:
A circuit group control system which receives from a master processor a first command sequence and a second command sequence each of which is composed of a plurality of commands, each command being to be executed by one of a plurality of circuits, and causes any available circuits to execute the commands one by one in order of arrangement in each command sequence. The circuit group control system achieves concurrent execution of a plurality of command sequences by causing a circuit (a second circuit) to execute a command in the second command sequence while another circuit (a first circuit) is executing another command in the first command sequence.
摘要:
A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.
摘要:
An information processing apparatus performs switching between an exception handler and normal processing. The information processing apparatus includes a processor a data processing unit that performs a particular processing upon receiving a processing request from the processor; an interrupt controller that issues an interrupt request to the processor; and an exception control unit that controls the interrupt controller, wherein the data processing unit is connected with the exception control unit via a dedicated line. The data processing unit includes a notification unit that notifies, via the dedicated line, the exception control unit of status information indicating current status of the data processing unit, and based on the notified status information and setup information set by the processor, the exception control unit judges whether to cause the interrupt controller to issue to the processor an interrupt request to execute an exception handler.