公开(公告)号：US20100276795A1

公开(公告)日：2010-11-04

申请号：US12493321

申请日：2009-06-29

申请人： Ho Young SON ,  Jun Gi CHOI ,  Seung Taek YANG

发明人： Ho Young SON ,  Jun Gi CHOI ,  Seung Taek YANG

IPC分类号： H01L23/52 ,  H01L21/50 ,  H01L21/60 ,  H01L23/48

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/29 ,  H01L25/50 ,  H01L2224/05547 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2225/06541 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2224/05552

摘要： A semiconductor package capable of being efficiently stacked and a method of manufacturing the same is presented. The semiconductor package includes a semiconductor chip, an insulation layer, and a through-electrode. The semiconductor chip has a first surface and a second surface, a circuit section in the semiconductor chip, an internal circuit pattern electrically connected to the circuit section, and a through-hole that passes through the internal circuit pattern and through the first and second surfaces. The insulation layer is on a through-hole of the semiconductor chip and has an opening which exposes the internal circuit pattern which was exposed by the through-hole. The through-electrode is in the through-hole and electrically coupled to the internal circuit pattern which is exposed through the opening of the insulation layer.

摘要翻译： 提出了一种能够有效堆叠的半导体封装及其制造方法。 半导体封装包括半导体芯片，绝缘层和通孔。 半导体芯片具有第一表面和第二表面，半导体芯片中的电路部分，电连接到电路部分的内部电路图案，以及穿过内部电路图案并穿过第一和第二表面的通孔 。 绝缘层位于半导体芯片的通孔上，并且具有露出由通孔露出的内部电路图案的开口。 贯通电极在通孔中并且电耦合到通过绝缘层的开口暴露的内部电路图案。

公开(公告)号：US20110246104A1

公开(公告)日：2011-10-06

申请号：US12839356

申请日：2010-07-19

申请人： Jae Bum KO ,  Jun Gi CHOI

发明人： Jae Bum KO ,  Jun Gi CHOI

IPC分类号： G06F19/00

CPC分类号： G11C8/12 ,  G11C29/785 ,  G11C29/883 ,  H01L2225/06527

摘要： A semiconductor apparatus includes an individual chip designating code setting block configured to generate a plurality of individual chip designating code of different values; an individual chip activation block configured to enable an individual chip activation signal among a plurality of individual chip activation signals, which corresponds to individual chip designating code, when the individual chip designating code matches the individual chip control code; and a control block configured to set the individual chip control code or output chip selection address as the individual chip control code in response to chip selection fuse signals and test fuse signals.

摘要翻译： 一种半导体装置，包括单独的芯片指定代码设置块，其被配置为生成不同值的多个独立芯片指定代码; 单个芯片激活块，其被配置为当各个芯片指定代码与单独的芯片控制代码匹配时，使多个独立芯片激活信号中的各个芯片激活信号对应于各个芯片指定代码; 以及控制块，被配置为响应于芯片选择熔丝信号和测试熔丝信号，将单独的芯片控制代码或输出芯片选择地址设置为单独的芯片控制代码。

公开(公告)号：US20110234303A1

公开(公告)日：2011-09-29

申请号：US12841106

申请日：2010-07-21

申请人： Jun Gi CHOI

发明人： Jun Gi CHOI

IPC分类号： H01H37/76

CPC分类号： H01L23/5256 ,  G11C17/18 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse circuit includes an electric fuse coupled to a first voltage source; a low resistance unit coupled to the electric fuse and having a junction which is capable of breaking down; and a switching unit coupled between the low resistance unit and a second voltage source.

摘要翻译： 熔丝电路包括耦合到第一电压源的电熔丝; 耦合到电熔丝并具有能够分解的结的低电阻单元; 以及耦合在所述低电阻单元和第二电压源之间的开关单元。

公开(公告)号：US20110006839A1

公开(公告)日：2011-01-13

申请号：US12886768

申请日：2010-09-21

申请人： Jun Gi CHOI

发明人： Jun Gi CHOI

IPC分类号： H03K5/00

CPC分类号： G11C5/147 ,  G11C7/02 ,  G11C7/065 ,  G11C7/08 ,  G11C8/18 ,  G11C11/4074 ,  G11C11/4091

摘要： The present invention discloses a circuit providing a power for a sense amplifier that stabilizes a power voltage supplied to the sense amplifier by compensating a noise generated in the power voltage when the sense amplifier operates with an selectively generated decoupling noise. The circuit providing a power for a sense amplifier includes a sense amplifying circuit sensing and amplifying data loaded on a bit line with a first power. A power supplying unit provides the first power to the sense amplifying circuit. A decoupling unit generates a decoupling noise with a second power and provides the decoupling noise to the first power voltage. The decoupling noise is maintained for a period including a time point of an operation of the sense amplifying circuit and a predetermined time thereafter.

摘要翻译： 本发明公开了一种提供用于感测放大器的电源的电路，其通过补偿当读出放大器以选择性地产生的解耦噪声工作时在电源电压中产生的噪声来稳定提供给读出放大器的电源电压。 提供用于读出放大器的电源的电路包括感测放大电路，以感测和放大加载在具有第一功率的位线上的数据。 供电单元向感测放大电路提供第一功率。 解耦单元产生具有第二功率的去耦噪声，并将解耦噪声提供给第一电源电压。 解耦噪声保持包括感测放大电路的操作的时间点和之后的预定时间的周期。

公开(公告)号：US20090161463A1

公开(公告)日：2009-06-25

申请号：US12136196

申请日：2008-06-10

申请人： Jun Gi CHOI

发明人： Jun Gi CHOI

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C5/147 ,  G11C7/02 ,  G11C7/065 ,  G11C7/08 ,  G11C8/18 ,  G11C11/4074 ,  G11C11/4091

摘要： The present invention discloses a circuit providing a power for a sense amplifier that stabilizes a power voltage supplied to the sense amplifier by compensating a noise generated in the power voltage when the sense amplifier operates with an selectively generated decoupling noise. The circuit providing a power for a sense amplifier includes a sense amplifying circuit sensing and amplifying data loaded on a bit line with a first power. A power supplying unit provides the first power to the sense amplifying circuit. A decoupling unit generates a decoupling noise with a second power and provides the decoupling noise to the first power voltage. The decoupling noise is maintained for a period including a time point of an operation of the sense amplifying circuit and a predetermined time thereafter.

摘要翻译： 本发明公开了一种提供用于感测放大器的电源的电路，其通过补偿当读出放大器以选择性地产生的解耦噪声工作时在电源电压中产生的噪声来稳定提供给读出放大器的电源电压。 提供用于读出放大器的电源的电路包括感测放大电路，以感测和放大加载在具有第一功率的位线上的数据。 供电单元向感测放大电路提供第一功率。 解耦单元产生具有第二功率的去耦噪声，并将解耦噪声提供给第一电源电压。 解耦噪声保持包括感测放大电路的操作的时间点和之后的预定时间的周期。