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    Apparatus and manufacturing method
    2.
    发明授权
    Apparatus and manufacturing method 有权

    公开(公告)号：US10784181B2

    公开(公告)日：2020-09-22

    申请号：US15905044

    申请日：2018-02-26

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： HuiLi Fu ,  Jyh Rong Lin ,  Shujie Cai

    IPC: H01L23/373 ,  H01L23/42 ,  H01L21/48 ,  H01L23/367

    Abstract: An apparatus includes a circuit device, a heat sink fin, and a thermal interface material layer. The thermal interface material layer is thermally coupled to the circuit device and the heat sink fin. The thermal interface material layer includes a first alloy layer, a nanometal particle layer, and a second alloy layer. The first alloy layer is thermally coupled to the circuit device. The nanometal particle layer is thermally coupled to the first alloy layer. The nanometal particle layer includes nanometal particles and an intermediate mixture.

    Chip package structure and manufacturing method thereof
    3.
    发明授权
    Chip package structure and manufacturing method thereof 有权

    公开(公告)号：US10903135B2

    公开(公告)日：2021-01-26

    申请号：US15855752

    申请日：2017-12-27

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： HuiLi Fu ,  Shujie Cai ,  Xiao Hu

    IPC: H01L23/373 ,  H01L25/00 ,  H01L25/065 ,  H01L23/31 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00

    Abstract: A chip package structure, including a substrate, multiple chips and multiple discrete devices that are packaged on an upper surface of the substrate, and a heat dissipation apparatus, where the heat dissipation apparatus includes an insulation layer and a thermally conductive layer that are laminated. The insulation layer completely encloses and adheres to outer surfaces of the multiple chips, outer surfaces of the multiple discrete devices, and the upper surface of the substrate and configured to conduct heat generated by the multiple chips and the multiple discrete devices to the thermally conductive layer and the substrate such that the heat generated by the multiple chips and the multiple discrete devices dissipated using the thermally conductive layer and the substrate.

    Integrated circuit die and manufacture method thereof
    4.
    发明授权
    Integrated circuit die and manufacture method thereof 有权

    公开(公告)号：US10607913B2

    公开(公告)日：2020-03-31

    申请号：US15797549

    申请日：2017-10-30

    Applicant: HUAWEI TECHNOLOGIES CO., LTD.

    Inventor： HuiLi Fu ,  Shujie Cai ,  Feiyu Luo

    IPC: H01L23/36 ,  H01L23/367 ,  H01L21/02 ,  H01L21/768 ,  H01L23/31 ,  H01L23/528 ,  H01L23/00

    Abstract: The present invention provide an IC die, including an underlay; an active component; an interconnection layer, covering the active component, where the interconnection layer includes multiple metal layers and multiple dielectric layers, the multiple metal layers and the multiple dielectric layers are alternately arranged, a metal layer whose distance to the active component is the farthest in the multiple metal layers includes metal cabling and a metal welding pad; and a heat dissipation layer, where the heat dissipation layer covers a region above the interconnection layer except a position corresponding to the metal welding pad, the heat dissipation layer is located under a package layer, the package layer includes a plastic packaging material, and the heat dissipation layer includes an electrical-insulating material whose heat conductivity is greater than a preset value.

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