公开(公告)号：US20190294442A1

公开(公告)日：2019-09-26

申请号：US16439335

申请日：2019-06-12

Applicant: Huawei Technologies Co., Ltd.

Inventor： Lei FANG ,  Xi CHEN ,  Weiguang CAI

IPC: G06F9/30 ,  G06F13/16

Abstract: A computer system and a memory access technology are provided. In the computer system, when load/store instructions having a dependency relationship is processed, dependency information between a producer load/store instruction and a consumer load/store instruction can be obtained from a processor. A consumer load/store request is sent to a memory controller in the computer system based on the obtained dependency information, so that the memory controller can terminate a dependency relationship between load/store requests in the memory controller locally based on the dependency information in the received consumer load/store request, and execute the consumer load/store request.

公开(公告)号：US20180101475A1

公开(公告)日：2018-04-12

申请号：US15839665

申请日：2017-12-12

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Lei FANG ,  Xiongli GU ,  Weiguang CAI

IPC: G06F12/0817 ,  G06F12/0808 ,  G06F12/084

CPC classification number: G06F12/0817 ,  G06F12/0808 ,  G06F12/082 ,  G06F12/084 ,  G06F12/121 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/62

Abstract: Embodiments of the present disclosure disclose a method for combining entries, including: determining N to-be-combined entries, where a cache block indicated by an entry label of each entry of the N entries belongs to a combination range, and the combination range indicates 2a cache blocks; and combining the N entries into a first entry, where an entry label of the first entry indicates the 2a cache blocks, and a sharer number of the first entry includes a sharer number of each entry of the N entries. According to the method, entries in a directory can be combined effectively, thereby improving directory usage efficiency.

公开(公告)号：US20170364442A1

公开(公告)日：2017-12-21

申请号：US15675929

申请日：2017-08-14

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Xiongli GU ,  Lei FANG ,  Weiguang CAI ,  Peng LIU

IPC: G06F12/0817 ,  G06F12/0846 ,  G06F12/084 ,  G06F12/0864 ,  G06F12/0811

CPC classification number: G06F12/0822 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0817 ,  G06F12/0828 ,  G06F12/084 ,  G06F12/0846 ,  G06F12/0864 ,  G06F2212/1044 ,  G06F2212/283 ,  G06F2212/314 ,  G06F2212/6032 ,  G06F2212/621

Abstract: The present disclosure discloses a method for accessing a data visitor directory in a multi-core system, a directory cache device, a multi-core system, and a directory storage unit. The method includes: receiving a first access request sent by a first processor core, where the first access request is used to access an entry, corresponding to a first data block, in a directory; determining, according to the first access request, that a single-pointer entry array has a first single-pointer entry corresponding to the first data block; when determining, according to the first single-pointer entry, that a sharing entry array has a first sharing entry associated with the first single-pointer entry, determining multiple visitors of the first data block according to the first sharing entry. According to embodiments of the present disclosure, storage resources occupied by a directory can be reduced.

公开(公告)号：US20130111142A1

公开(公告)日：2013-05-02

申请号：US13719626

申请日：2012-12-19

Applicant: Huawei Technologies Co., Ltd.

Inventor： Wei ZHENG ,  Jiangen LIU ,  Gang LIU ,  Weiguang CAI

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F12/0806 ,  G06F12/0811 ,  G06F2212/1012

Abstract: Embodiments of the present invention disclose a method for accessing a cache and a pseudo cache agent (PCA). The method of the present invention is applied to a multiprocessor system, where the system includes at least one NC, at least one PCA conforming to a processor micro-architecture level interconnect protocol is embedded in the NC, the PCA is connected to at least one PCA storage device, and the PCA storage device stores data shared among memories in the multiprocessor system. The method of the present invention includes: if the NC receives a data request, obtaining, by the PCA, target data required in the data request from the PCA storage device connected to the PCA; and sending the target data to a sender of the data request. Embodiments of the present invention are mainly applied to a process of accessing cache data in the multiprocessor system.

Abstract translation: 本发明的实施例公开了一种用于访问高速缓存和伪高速缓存代理（PCA）的方法。 本发明的方法应用于多处理器系统，其中系统包括至少一个NC，至少一个符合处理器微架构级互连协议的PCA嵌入在NC中，PCA连接到至少一个 PCA存储装置，PCA存储装置将存储在多处理器系统中的数据共享。 本发明的方法包括：如果NC接收到数据请求，则由PCA从连接到PCA的PCA存储设备获得数据请求中所需的目标数据; 并将目标数据发送到数据请求的发送者。 本发明的实施例主要应用于在多处理器系统中访问高速缓存数据的过程。

公开(公告)号：US20190108134A1

公开(公告)日：2019-04-11

申请号：US16211225

申请日：2018-12-05

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Weiguang CAI ,  Xiongli GU ,  Lei FANG

IPC: G06F12/1027

Abstract: A method for accessing an entry in a translation lookaside buffer and a processing chip are provided. In the method, the entry includes at least one combination entry, and the combination entry includes a virtual huge page number, a bit vector field, and a physical huge page number. The physical huge page number is an identifier of N consecutive physical pages corresponding to the N consecutive virtual pages. One entry is used to represent a plurality of virtual-to-physical page mappings, so that when a page table length is fixed, a quantity of entries in the TLB can be increased exponentially, thereby increasing a TLB hit probability, and reducing TLB misses. In this way, a delay in program processing can be reduced, and processing efficiency of the processing chip can be improved.

公开(公告)号：US20190073315A1

公开(公告)日：2019-03-07

申请号：US16178676

申请日：2018-11-02

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Lei FANG ,  Weiguang CAI ,  Xiongli GU

IPC: G06F12/1027 ,  G06F12/1009 ,  G06F12/0842

CPC classification number: G06F12/1027 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0842 ,  G06F12/1009 ,  G06F12/128 ,  G06F2212/684

Abstract: A translation lookaside buffer (TLB) management method and a multi-core processor are provided. the method includes: receiving, by a first core, a first address translation request; querying a TLB of the first core based on the first address translation request; determining that a first target TLB entry corresponding to the first address translation request is missing in the TLB of the first core, obtaining the first target TLB entry; determining that entry storage in the TLB of the first core is full; determining a second core from cores in an idle state in the multi-core processor; replacing a first entry in the TLB of the first core with the first target TLB entry; storing the first entry in a TLB of the second core. Thereby reducing a TLB miss rate and accelerating program execution.